A simulated annealing approach with sequence-pair encoding using a penalty function for the placement problem with boundary constraints

2003 ◽  
Author(s):  
S. Tayu
Keyword(s):  
Simulated Annealing ◽  
Penalty Function ◽  
Sequence Pair ◽  
Placement Problem ◽  
Boundary Constraints

scholarly journals A Fast Clustering-Based Min-Cut Placement Algorithm With Simulated-Annealing Performance

VLSI Design ◽  
1996 ◽  
Vol 5 (1) ◽  
pp. 37-48 ◽  
Author(s):  
Youssef Saab
Keyword(s):  
Simulated Annealing ◽  
Integrated Circuits ◽  
Large Scale ◽  
Optimization Problem ◽  
Wire Length ◽  
Constrained Optimization Problem ◽  
Placement Problem ◽  
Constructive Methods ◽  
Placement Algorithm ◽  
Min Cut

Placement is an important constrained optimization problem in the design of very large scale (VLSI) integrated circuits [1–4]. Simulated annealing [5] and min-cut placement [6] are two of the most successful approaches to the placement problem. Min-cut methods yield less congested and more routable placements at the expense of more wire-length, while simulated annealing methods tend to optimize more the total wire-length with little emphasis on the minimization of congestion. It is also well known that min-cut algorithms are substantially faster than simulated-annealing-based methods. In this paper, a fast min-cut algorithm (ROW-PLACE) for row-based placement is presented and is empirically shown to achieve simulated-annealing-quality wire-length on a number of benchmark circuits. In comparison with Timberwolf 6 [7], ROW-PLACE is at least 12 times faster in its normal mode and is at least 25 times faster in its faster mode. The good results of ROW-PLACE are achieved using a very effective clustering-based partitioning algorithm in combination with constructive methods that reduce the wire-length of nets involved in terminal propagation.

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