scholarly journals A Fast Clustering-Based Min-Cut Placement Algorithm With Simulated-Annealing Performance

VLSI Design ◽  
1996 ◽  
Vol 5 (1) ◽  
pp. 37-48 ◽  
Author(s):  
Youssef Saab
Keyword(s):  
Simulated Annealing ◽  
Integrated Circuits ◽  
Large Scale ◽  
Optimization Problem ◽  
Wire Length ◽  
Constrained Optimization Problem ◽  
Placement Problem ◽  
Constructive Methods ◽  
Placement Algorithm ◽  
Min Cut

Placement is an important constrained optimization problem in the design of very large scale (VLSI) integrated circuits [1–4]. Simulated annealing [5] and min-cut placement [6] are two of the most successful approaches to the placement problem. Min-cut methods yield less congested and more routable placements at the expense of more wire-length, while simulated annealing methods tend to optimize more the total wire-length with little emphasis on the minimization of congestion. It is also well known that min-cut algorithms are substantially faster than simulated-annealing-based methods. In this paper, a fast min-cut algorithm (ROW-PLACE) for row-based placement is presented and is empirically shown to achieve simulated-annealing-quality wire-length on a number of benchmark circuits. In comparison with Timberwolf 6 [7], ROW-PLACE is at least 12 times faster in its normal mode and is at least 25 times faster in its faster mode. The good results of ROW-PLACE are achieved using a very effective clustering-based partitioning algorithm in combination with constructive methods that reduce the wire-length of nets involved in terminal propagation.

scholarly journals Learning Compact Model for Large-Scale Multi-Label Data

2019 ◽  
Vol 33 ◽  
pp. 5385-5392 ◽  
Author(s):  
Tong Wei ◽  
Yu-Feng Li
Keyword(s):  
Large Scale ◽  
Optimization Problem ◽  
Performance Metrics ◽  
State Of The Art ◽  
Optimization Method ◽  
Model Parameters ◽  
Generalization Capability ◽  
Constrained Optimization Problem ◽  
Unseen Data ◽  
Model Size

Large-scale multi-label learning (LMLL) aims to annotate relevant labels from a large number of candidates for unseen data. Due to the high dimensionality in both feature and label spaces in LMLL, the storage overheads of LMLL models are often costly. This paper proposes a POP (joint label and feature Parameter OPtimization) method. It tries to filter out redundant model parameters to facilitate compact models. Our key insights are as follows. First, we investigate labels that have little impact on the commonly used LMLL performance metrics and only preserve a small number of dominant parameters for these labels. Second, for the remaining influential labels, we reduce spurious feature parameters that have little contribution to the generalization capability of models, and preserve parameters for only discriminative features. The overall problem is formulated as a constrained optimization problem pursuing minimal model size. In order to solve the resultant difficult optimization, we show that a relaxation of the optimization can be efficiently solved using binary search and greedy strategies. Experiments verify that the proposed method clearly reduces the model size compared to state-of-the-art LMLL approaches, in addition, achieves highly competitive performance.

scholarly journals IC Floorplanning Optimization using Simulated Annealing with Order-based Representation

2021 ◽  
Vol 13 (2) ◽  
pp. 62-70
Author(s):  
Rajendra Bahadur Singh ◽  
◽  
Anurag Singh Baghel
Keyword(s):  
Simulated Annealing ◽  
Integrated Circuits ◽  
Integrated Circuit ◽  
Simulated Annealing Algorithm ◽  
Research Work ◽  
Second Phase ◽  
Wire Length ◽  
Annealing Algorithm ◽  
Two Phases ◽  
Physical Quantities

Integrated Circuits (IC) floorplanning is an important step in the integrated circuit physical design; it influences the area, wire-length, delay etc of an IC. In this paper, Order Based (OB) representation has been proposed for fixed outline floorplan with Simulated Annealing (SA) algorithm. To optimize the IC floorplan, two physical quantities have been considered such as area, and wire-length for hard IP modules. Optimization of the IC floorplan works in two phases. In the first phase, floorplans are constructed by proposed representation without any overlapping among the modules. In the second phase, Simulated Annealing algorithm explores the packing of all modules in floorplan to find better optimal performances i.e. area and wire-length. The Experimental results on Microelectronic Center of North Carolina benchmark circuits show that our proposed representation with SA algorithm performs better for area and wire-length optimization than the other methods. The results are compared with the solutions derived from other algorithms. The significance of this research work is improvement in optimized area and wire-length for modern IC.

Application of Chaotic Univariate Marginal Distribution Algorithm to Economic Dispatch Control of Cascade Hydropower Plants

2012 ◽  
Vol 516-517 ◽  
pp. 1326-1331
Author(s):  
Wei Gu ◽  
Yong Gang Wu ◽  
Jin Cheng Wu
Keyword(s):  
Large Scale ◽  
Optimization Problem ◽  
Marginal Distribution ◽  
Economic Dispatch ◽  
Constrained Optimization Problem ◽  
Chaotic Search ◽  
Chaotic Sequences ◽  
Hydropower Plants ◽  
Simulation Results ◽  
Linear Constrained Optimization

The economic dispatch control of cascade hydropower plants is a large scale non-linear constrained optimization problem, which plays an important role in cascade reservoirs daily optimal. This paper proposes a chaotic univariate marginal distribution algorithm (CUMDA) to solve the economic dispatch problem of cascade hydropower plants. In the proposed method, a chaotic search is integrated with univariate marginal distribution algorithm (UMDA) to effectively avoid premature convergence, chaotic sequences combine with adaptive approach are applied to help algorithm escape from local optimal trap. The feasibility of the proposed method is demonstrated for economic dispatch control of a test cascade hydro system. The simulation results show that the proposed method can obtain higher quality solution.

scholarly journals A Swarm Random Walk Based Method for the Standard Cell Placement Problem

2014 ◽  
Vol 2014 ◽  
pp. 1-11 ◽  
Author(s):  
Najwa Altwaijry ◽  
Mohamed El Bachir Menai
Keyword(s):  
Simulated Annealing ◽  
Random Walk ◽  
Hybrid Methods ◽  
Vlsi Design ◽  
Standard Cell ◽  
Placement Problem ◽  
Benchmark Suite ◽  
Cell Placement ◽  
On Chip ◽  
Min Cut

The standard cell placement (SCP) problem is a well-studied placement problem, as it is an important step in the VLSI design process. In SCP, cells are placed on chip to optimize some objectives, such as wirelength or area. The SCP problem is solved using mainly four basic methods: simulated annealing, quadratic placement, min-cut placement, and force-directed placement. These methods are adequate for small chip sizes. Nowadays, chip sizes are very large, and hence, hybrid methods are employed to solve the SCP problem instead of the original methods by themselves. This paper presents a new hybrid method for the SCP problem using a swarm intelligence-based (SI) method, called SwarmRW (swarm random walk), on top of a min-cut based partitioner. The resulting placer, called sPL (swarm placer), was tested on the PEKU benchmark suite and compared with several related placers. The obtained results demonstrate the effectiveness of the proposed approach and show that sPL can achieve competitive performance.

scholarly journals New Three-Level Resource Management Enhancing Quality of Offline Hardware Task Placement on FPGA

2010 ◽  
Vol 2010 ◽  
pp. 1-20 ◽  
Author(s):  
Ikbel Belaid ◽  
Fabrice Muller ◽  
Maher Benjemaa
Keyword(s):  
Resource Management ◽  
Resource Utilization ◽  
Optimization Problem ◽  
Branch And Bound Method ◽  
Constrained Optimization Problem ◽  
Placement Problem ◽  
Efficient Management ◽  
Task Placement ◽  
Heterogeneous Resources

Currently, reconfigurable hardware devices feature a high density of heterogeneous resources to enable multitasking and offer flexibility in application needs. These concepts raise the need for efficient management of hardware tasks and hardware resources. The scheduling of hardware tasks is highly dependent on placement. Placement focuses on allocation of hardware resources required by the scheduled hardware tasks. In this paper, we propose novel three-level resource management that investigates enhancement of placement quality by reducing task rejection, configuration overheads, and by optimizing resource utilization. Improving placement quality will produce significant enhancement of performance for scheduling and overall execution time of the application in FPGA. Hence, the placement problem is formulated into a constrained optimization problem and resolved with powerful solvers using the Branch and Bound method. The obtained results of an application of heterogeneous hardware tasks show an average resource utilization of 36% of the available resources on the reconfigurable region and an overall overhead of 11% of total application running time, and we have eliminated the issue of task rejection. Compared to static implementation, the gain in resource utilization within the reconfigurable region achieves up to 43%.

scholarly journals 3D-Via Driven Partitioning for 3D VLSI Integrated Circuits

2010 ◽  
Vol 13 (3) ◽  
Author(s):  
Sandro Sawicki ◽  
Gustavo Wilke ◽  
Marcelo Johann ◽  
Ricardo Reis
Keyword(s):  
Integrated Circuits ◽  
Circuit Design ◽  
Graph Partitioning ◽  
State Of The Art ◽  
Placement Problem ◽  
New Approach ◽  
Graph Partitioning Problem ◽  
Circuit Structure ◽  
Partitioning Problem ◽  
Min Cut

A 3D circuit is the stacking of regular 2D circuits. The advances on the fabrication and packaging technologies allowed interconnecting stacked 2D circuits by using 3D vias. However, 3D-vias can impose significant obstacles and constraints to the 3D placement problem. Most of the existing placement algorithms completely ignore this fact, but they do optimize the number of vias using a min-cut partitioning applied to a generic graph partitioning problem. This work proposes a new approach for I/O pads and cells partitioning addressing 3D-vias reduction and its impact on the 3D circuit design. The approach presents two distinct strategies: the first one is based on circuit structure analyses and the second one reducing the number of connections between non-adjacent tiers. The strategies outperformed a state-of-the-art hypergraph partitioner, hMetis [8] in the number of 3D-vias 19%, 17%, 12% and 16% using two, three, four and five tiers.

scholarly journals A Simulated Annealing Based Centre of Mass (SAC) Approach for Mesh Routers Placement in Rural Areas

2020 ◽  
Vol 11 (1) ◽  
pp. 37-65
Author(s):  
Jean Louis Kedieng Ebongue Fendji ◽  
Chris Thron
Keyword(s):  
Simulated Annealing ◽  
Rural Areas ◽  
Large Scale ◽  
Mesh Network ◽  
Convergence Time ◽  
Centre Of Mass ◽  
Placement Problem ◽  
Solution Quality ◽  
Wireless Mesh ◽  
Area Of Interest

The problem of node placement in a rural wireless mesh network (RWMN) consists of determining router placement which minimizes the number of routers while providing good coverage of the area of interest. This problem is NP-hard with a factorial complexity. This article introduces a new approach, called the simulated annealing-based centre of mass (SAC) for solving this placement problem. The intent of this approach is to improve the robustness and the quality of solution, and to minimize the convergence time of a simulated annealing (SA) approach in solving the same problem in small and large scale. SAC is compared to the centre of mass (CM) and simulated annealing (SA) approaches. The performances of these algorithms were evaluated on a set of 24 instances. The experimental results show that the SAC approach provides the best robustness and solution quality, while decreasing by half the convergence time of the SA algorithm.

scholarly journals Simulated annealing method for equilibrium placement problem

2021 ◽  
pp. 152-158
Author(s):  
Igor Kozin ◽  
Natalia Maksyshko ◽  
Yaroslav Tereshko
Keyword(s):  
Simulated Annealing ◽  
Optimization Problem ◽  
Simulated Annealing Algorithm ◽  
Optimal Solution ◽  
Placement Problem ◽  
Fragmentary Structure ◽  
Simulating Annealing ◽  
Set Of Permutations ◽  
Annealing Algorithm ◽  
The Traveling Salesman Problem

The paper proposes a modification of the simulated annealing algorithm as applied to problems that have a fragmented structure. An algorithm for simulating annealing for the traveling salesman problem is considered and its applicability to the optimization problem on a set of permutations is shown. It is proved that the problem of equilibrium placement of point objects on a plane has a fragmentary structure and, therefore, reduces to an optimization problem on a set of permutations. The results of numerical experiments for various types of algorithms for finding the optimal solution in the equilibrium placement problem are presented.

scholarly journals Selective Simulated Annealing for Large Scale Airspace Congestion Mitigation

Aerospace ◽  
2021 ◽  
Vol 8 (10) ◽  
pp. 288
Author(s):  
Julien Lavandier ◽  
Arianit Islami ◽  
Daniel Delahaye ◽  
Supatcha Chaimatanan ◽  
Amir Abecassis
Keyword(s):  
Simulated Annealing ◽  
Combinatorial Optimization ◽  
Assignment Problem ◽  
Large Scale ◽  
Optimization Problem ◽  
Traffic Assignment ◽  
Combinatorial Optimization Problem ◽  
Slot Allocation ◽  
Traffic Assignment Problem ◽  
Aircraft Trajectories

This paper presents a methodology to minimize the airspace congestion of aircraft trajectories based on slot allocation techniques. The traffic assignment problem is modeled as a combinatorial optimization problem for which a selective simulated annealing has been developed. Based on the congestion encountered by each aircraft in the airspace, this metaheuristic selects and changes the time of departure of the most critical flights in order to target the most relevant aircraft. The main objective of this approach is to minimize the aircraft speed vector disorder. The proposed algorithm was implemented and tested on simulated trajectories generated with real flight plans on a day of traffic over French airspace with 8800 flights.

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