Post-chemical-mechanical planarization cleaning application in metallization

2002 ◽  
Author(s):  
C. Huynh ◽  
J. Chapple-Sokoi ◽  
K. Pope
Keyword(s):  
Chemical Mechanical Planarization

A Latent Issue of Via Resistance: Mechanism and Solution

2018 ◽  
Author(s):  
Wentao Qin ◽  
Scott Donaldson ◽  
Dan Rogers ◽  
Lahcen Boukhanfra ◽  
Julien Thiefain ◽  
...  
Keyword(s):  
Thermal Stress ◽  
Chemical Mechanical Planarization ◽  
Resistance Mechanism ◽  
Formation Enthalpy ◽  
Metal Line ◽  
Device Failure ◽  
Valence Electrons ◽  
Wafer Processing ◽  
Field Failure ◽  
And Tungsten

Abstract Many semiconductor products are manufactured with mature technologies involving the uses of aluminum (Al) lines and tungsten (W) vias. High resistances of the vias were sometimes observed only after electrical or thermal stress. A layer of Ti oxide was found on such a via. In the wafer processing, the post W chemical mechanical planarization (WCMP) cleaning left residual W oxide on the W plugs. Ti from the overlaying metal line spontaneously reduced the W oxide, through which Ti oxide formed. Compared with W oxide, the Ti oxide has a larger formation enthalpy, and the valence electrons of Ti are more tightly bound to the O ion cores. As a result, the Ti oxide is more resistive than the W oxide. Consequently, the die functioned well in the first test in the fab, but the via resistance increased significantly after a thermal stress, which led to device failure in the second test. The NH4OH concentration was therefore increased to more effectively remove residual W oxide, which solved the problem. The thermal stress had prevented the latent issue from becoming a more costly field failure.

A Proof for the Possibility of Ce-Oxide from CMP Residuals in Si-Wafers by Analytical TEM

2012 ◽  
Author(s):  
Wayne Zhao ◽  
Liem Do Thanh ◽  
Michael Gribelyuk ◽  
Mary-Ann Zaitz ◽  
Wing Lai
Keyword(s):  
Technology Development ◽  
Early Stage ◽  
Chemical Mechanical Planarization ◽  
Particle Cluster ◽  
Limited Region ◽  
Physical Evidence ◽  
Analytical Tem ◽  
Transmission Electron ◽  
Oxide Particles

Abstract Inclusion of cerium (Ce) oxide particles as an abrasive into chemical mechanical planarization (CMP) slurries has become popular for wafer fabs below the 45nm technology node due to better polishing quality and improved CMP selectivity. Transmission electron microscopy (TEM) has difficulties finding and identifying Ce-oxide residuals due to the limited region of analysis unless dedicated efforts to search for them are employed. This article presents a case study that proved the concept in which physical evidence of Ce-rich particles was directly identified by analytical TEM during a CMP tool qualification in the early stage of 20nm node technology development. This justifies the need to setup in-fab monitoring for trace amounts of CMP residuals in Si-based wafer foundries. The fact that Cr resided right above the Ce-O particle cluster, further proved that the Ce-O particles were from the wafer and not introduced during the sample preparation.

scholarly journals A Resonant Pressure Microsensor with a Wide Pressure Measurement Range

Micromachines ◽  
2021 ◽  
Vol 12 (4) ◽  
pp. 382
Author(s):  
Chao Xiang ◽  
Yulan Lu ◽  
Chao Cheng ◽  
Junbo Wang ◽  
Deyong Chen ◽  
...  
Keyword(s):  
Chemical Mechanical Planarization ◽  
Measurement Range ◽  
Silicon On Insulator ◽  
Anodic Bonding ◽  
Pressure Measurements ◽  
Quality Factors ◽  
Deep Reactive Ion Etching ◽  
Wide Range ◽  
Form Pressure ◽  
Silicon Islands

This paper presents a resonant pressure microsensor with a wide range of pressure measurements. The developed microsensor is mainly composed of a silicon-on-insulator (SOI) wafer to form pressure-sensing elements, and a silicon-on-glass (SOG) cap to form vacuum encapsulation. To realize a wide range of pressure measurements, silicon islands were deployed on the device layer of the SOI wafer to enhance equivalent stiffness and structural stability of the pressure-sensitive diaphragm. Moreover, a cylindrical vacuum cavity was deployed on the SOG cap with the purpose to decrease the stresses generated during the silicon-to-glass contact during pressure measurements. The fabrication processes mainly contained photolithography, deep reactive ion etching (DRIE), chemical mechanical planarization (CMP) and anodic bonding. According to the characterization experiments, the quality factors of the resonators were higher than 15,000 with pressure sensitivities of 0.51 Hz/kPa (resonator I), −1.75 Hz/kPa (resonator II) and temperature coefficients of frequency of 1.92 Hz/°C (resonator I), 1.98 Hz/°C (resonator II). Following temperature compensation, the fitting error of the microsensor was within the range of 0.006% FS and the measurement accuracy was as high as 0.017% FS in the pressure range of 200 ~ 7000 kPa and the temperature range of −40 °C to 80 °C.

scholarly journals Novel Abrasive-Impregnated Pads and Diamond Plates for the Grinding and Lapping of Single-Crystal Silicon Carbide Wafers

2021 ◽  
Vol 11 (4) ◽  
pp. 1783
Author(s):  
Ming-Yi Tsai ◽  
Kun-Ying Li ◽  
Sun-Yu Ji
Keyword(s):  
Silicon Carbide ◽  
Wear Rate ◽  
Single Crystal ◽  
Traditional Method ◽  
Removal Rate ◽  
Chemical Mechanical Planarization ◽  
Single Crystal Silicon ◽  
Crystal Silicon ◽  
Diamond Grit ◽  
Ceramic Binder

In this study, special ceramic grinding plates impregnated with diamond grit and other abrasives, as well as self-made lapping plates, were used to prepare the surface of single-crystal silicon carbide (SiC) wafers. This novel approach enhanced the process and reduced the final chemical mechanical planarization (CMP) polishing time. Two different grinding plates with pads impregnated with mixed abrasives were prepared: one with self-modified diamond + SiC and a ceramic binder and one with self-modified diamond + SiO2 + Al2O3 + SiC and a ceramic binder. The surface properties and removal rate of the SiC substrate were investigated and a comparison with the traditional method was conducted. The experimental results showed that the material removal rate (MRR) was higher for the SiC substrate with the mixed abrasive lapping plate than for the traditional method. The grinding wear rate could be reduced by 31.6%. The surface roughness of the samples polished using the diamond-impregnated lapping plate was markedly better than that of the samples polished using the copper plate. However, while the surface finish was better and the grinding efficiency was high, the wear rate of the mixed abrasive-impregnated polishing plates was high. This was a clear indication that this novel method was effective and could be used for SiC grinding and lapping.

Chemical Mechanical Planarization Technology for Si Wafer Bonding

2019 ◽  
Vol 33 (10) ◽  
pp. 153-156
Author(s):  
JongHeun Lim ◽  
BoUn Yoon ◽  
KyungHyun Kim ◽  
YoungSun Ko ◽  
ChangJin Kang
Keyword(s):  
Wafer Bonding ◽  
Chemical Mechanical Planarization ◽  
Si Wafer

Advances in Chemical-Mechanical Planarization

MRS Bulletin ◽  
2002 ◽  
Vol 27 (10) ◽  
pp. 743-751 ◽  
Author(s):  
Rajiv K. Singh ◽  
Rajeev Bajaj
Keyword(s):  
Surface Topography ◽  
Process Integration ◽  
Semiconductor Industry ◽  
Chemical Mechanical Planarization ◽  
Shallow Trench Isolation ◽  
Trench Isolation ◽  
Fundamental Understanding ◽  
Copper Polishing ◽  
Future Growth

AbstractThe primary aim of this issue of MRS Bulletin is to present an overview of the materials issues in chemical–mechanical planarization (CMP), also known as chemical–mechanial polishing, a process that is used in the semiconductor industry to isolate and connect individual transistors on a chip. The CMP process has been the fastest-growing semiconductor operation in the last decade, and its future growth is being fueled by the introduction of copper-based interconnects in advanced microprocessors and other devices. Articles in this issue range from providing a fundamental understanding of the CMP process to the latest advancements in the field. Topics covered in these articles include an overview of CMP, fundamental principles of slurry design, understanding wafer–pad–slurry interactions, process integration issues, the formulation of abrasive-free slurries for copper polishing, understanding surface topography issues in shallow trench isolation, and emerging applications.

Step height removal mechanism of chemical mechanical planarization (CMP) for sub-nano-surface finish

Wear ◽  
2010 ◽  
Vol 268 (3-4) ◽  
pp. 505-510 ◽  
Author(s):  
Ji Chul Yang ◽  
Dong Won Oh ◽  
Gae Won Lee ◽  
Chang Lyung Song ◽  
Taesung Kim
Keyword(s):  
Surface Finish ◽  
Chemical Mechanical Planarization ◽  
Step Height ◽  
Removal Mechanism
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