Test chips, test systems, and thermal test data for multichip modules in the ESPRIT-APACHIP project

1994 ◽  
Vol 17 (3) ◽  
pp. 425-435 ◽  
Author(s):  
S.C. O'Mathuna ◽  
T. Fromont ◽  
W. Koschnick ◽  
L. O'Connor
Keyword(s):  
Test Data ◽  
Multichip Modules ◽  
Test Systems ◽  
Thermal Test ◽  
Test Chips

Stacked Chip Thermal Model Validation using Thermal Test Chips

2012 ◽  
Vol 2012 (1) ◽  
pp. 000873-000881
Author(s):  
Thomas Tarter ◽  
Bernie Siegal
Keyword(s):  
Model Validation ◽  
Thermal Model ◽  
Thermal Test ◽  
Test Chips

Assessing the Bearing Capacity of Hot-Metal Crane Ropes Based on Laboratory Thermal Test Data

Vestnik MEI ◽  
2018 ◽  
Vol 6 (6) ◽  
pp. 12-18
Author(s):  
Aleksandr N. Vorontsov ◽  
◽  
Vasiliy Yu. Volokhovsky ◽  
Vladimir I. Miroshnichenko ◽  
Vladimir V. Gaiduchenko ◽  
...  
Keyword(s):  
Bearing Capacity ◽  
Test Data ◽  
Hot Metal ◽  
Thermal Test

A Scalable Multi-Functional Thermal Test Chip Family: Design and Evaluation

2001 ◽  
Vol 123 (4) ◽  
pp. 323-330 ◽  
Author(s):  
Zs. Benedek ◽  
B. Courtois ◽  
G. Farkas ◽  
E. Kolla´r ◽  
S. Mir ◽  
...  
Keyword(s):  
Temperature Sensor ◽  
Thermal Characterization ◽  
Thermal Engineering ◽  
Test Chip ◽  
Basic Cell ◽  
Thermal Test ◽  
Wide Range ◽  
The Family ◽  
Test Chips

Nowadays, thermal characterization of IC packages and packaging technologies is becoming a key task in thermal engineering. To support this by measurements, we developed a family of thermal test chips that allow a wide range of possible applications. Our chips are based on the same basic cell that is mainly covered by dissipating resistors and also contains a temperature sensor. These basic cells are organized into arrays of different size. The arrays are designed such that further “super arrays” can also be built for tiling up larger package cavities. The first members of the family, TMC9 and TMC81, have been manufactured. Our measurements show that the goals aimed at the design have been achieved.

3D Integrated Packaging Approach for High Performance Processor-Memory Module

2013 ◽  
Vol 2013 (1) ◽  
pp. 000452-000457 ◽  
Author(s):  
S. C. Polzer ◽  
W. L. Wilkins ◽  
J. L. Fasig ◽  
M. J. Degerstrom ◽  
B. K. Gilbert ◽  
...  
Keyword(s):  
Thermal Management ◽  
High Performance ◽  
Mechanical Design ◽  
Power Delivery ◽  
Memory Module ◽  
Thermal Test ◽  
Power Delivery Network ◽  
3D Packaging ◽  
Test Chips ◽  
Delivery Network

As high performance computing (HPC) system performance requirements increase, it is necessary to investigate new methods for integrating system components. Of interest is the applicability of 3D packaging approaches to HPC systems. Using thermal test chips, we designed and assembled a 3D processor-memory module with an integrated power delivery network to investigate interconnect density, integration, testability, and rework issues with 3D integrated packaging in an HPC environment. The design was based on interconnection and power delivery requirements for a processor-memory module capable of supporting 64 full-duplex 30G SerDes, routing for 800 processor-to-memory pins, an integrated multi-tiered power delivery network, and a thermal management solution capable of dissipating a nominal processor heat flux of 100 W/cm2. The technologies selected—semi-rigid flex, power connectors, land grid array (LGA) attach with an anisotropic film, and cold plate-based cooling—are all commercially available technologies, which we adapted for this HPC module. As more advanced 3D packaging and integrated circuits become available, these assemblies and components can be incorporated into our approach to increase integration and performance. This design approach also accommodates substitution of thermal test chips in place of functional components, allowing validation of thermal management solutions ahead of the final module design. We will present the electrical-to-mechanical design strategy used to build this module and results of the thermal and electrical analyses, and point to several areas where further development work would be beneficial in the areas of interconnect, power delivery, and mechanical design.

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