Post-soft-breakdown characteristics of deep submicron NMOSFETs with ultrathin gate oxide

2001 ◽  
Vol 22 (7) ◽  
pp. 348-350 ◽  
Author(s):  
Min-Yu Tsai ◽  
Horng-Chih Lin ◽  
Da-Yuan Lee ◽  
Tiao-Yuan Huang
Keyword(s):  
Gate Oxide ◽  
Deep Submicron ◽  
Soft Breakdown

Modeling Soft Breakdown of Ultra-Thin Gate Oxide Layers

1999 ◽  
Vol 567 ◽  
Author(s):  
Michel Houssa ◽  
P.W. Mertens ◽  
M.M. Heyns
Keyword(s):  
Gate Voltage ◽  
Dielectric Breakdown ◽  
Percolation Cluster ◽  
Gate Oxide ◽  
Oxide Layers ◽  
Long Range Correlations ◽  
Electrical Stress ◽  
Non Gaussian ◽  
Thin Gate Oxide ◽  
Soft Breakdown

ABSTRACTThe time-dependent dielectric breakdown of MOS capacitors with ultra-thin gate oxide layers is investigated. After the occurrence of soft breakdown, the gate current increases by 3 to 4 orders of magnitudes and behaves like a power law of the applied gate voltage. It is shown that this behavior can be explained by assuming that a percolation path is formed between the electron traps generated in the gate oxide layer during electrical stress of the capacitors. The time dependence of the gate voltage signal after soft breakdown is next analysed. It is shown that the fluctuations in the gate voltage are non-gaussian as well as that long-range correlations exist in the system after soft breakdown. These results can be explained by a dynamic percolation model, taking into account the trapping-detrapping of charges within the percolation cluster formed at soft breakdown.

ESD reliability of thinner gate oxide in deep-submicron low-voltage CMOS technology

2002 ◽  
Author(s):  
Ming-Dou Ker ◽  
Chung-Yu Wu ◽  
Hun-Hsien Chang ◽  
Chien-Chang Huang ◽  
Chau-Neng Wu ◽  
...  
Keyword(s):  
Low Voltage ◽  
Gate Oxide ◽  
Cmos Technology ◽  
Deep Submicron

He plus remote plasma nitridation of ultra-thin gate oxide for deep submicron CMOS technology applications

2001 ◽  
Vol 37 (12) ◽  
pp. 788 ◽  
Author(s):  
Shyh-Fann Ting ◽  
Yean-Kuen Fang ◽  
Chien-Hao Chen ◽  
Chih-Wei Yang ◽  
Mo-Chiun Yu ◽  
...  
Keyword(s):  
Gate Oxide ◽  
Cmos Technology ◽  
Deep Submicron ◽  
Remote Plasma ◽  
Plasma Nitridation ◽  
Technology Applications ◽  
Submicron Cmos ◽  
Thin Gate Oxide

Gate oxide multiple soft breakdown (Multi-SBD) impact on CMOS inverter

2004 ◽  
Author(s):  
Huey-Ming Huang ◽  
C.Y. Ko ◽  
M.L. Yang ◽  
P.J. Liao ◽  
J.J. Wang ◽  
...  
Keyword(s):  
Gate Oxide ◽  
Cmos Inverter ◽  
Soft Breakdown

Passive Voltage Contrast Technique for Rapid In-Line Characterization and Failure Isolation During Development of Deep-Submicron ASIC CMOS Technology

1998 ◽  
Author(s):  
Victor Liang ◽  
Harlan Sur ◽  
Subhas Bothra
Keyword(s):  
Gate Oxide ◽  
Cmos Technology ◽  
Relative Magnitude ◽  
Deep Submicron ◽  
Process Step ◽  
First Case ◽  
Contrast Technique ◽  
Rapid Characterization ◽  
Voltage Contrast

Abstract Three case studies in which the passive voltage contrast technique (PVC) was used in-fab during the development of a 0.25mm ASIC CMOS technology for rapid characterization and failure isolation are presented. The first case involved using the PVC technique to evaluate the gate oxide quality at different points of the process, allowing for quick identification of the process steps that were damaging the gate oxide and the relative magnitude of the damage that each process step contributed. PVC was then used to perform in-line evaluation of the split lots that were ran to address the problem without having to pull wafers off the line for electrical testing. In the second case study, PVC was used in-line to identify the source of siliciderelated gate-to-source/drain leakage. At this point of the process, electrical probing was not possible, and PVC circumvented this problem. The third case involved using PVC to help identify a new failure mechanism for tungsten plug vias that manifested itself due to plasma charging and layout peculiarities related to deep submicron design rules.

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