Improvement in hot carrier lifetime as a function of N/sub 2/ ion implantation before gate oxide growth in deep submicron NMOS devices

1999 ◽  
Vol 20 (12) ◽  
pp. 602-604 ◽  
Author(s):  
F.J. Guarin ◽  
S.E. Rauch ◽  
G. La Rosa ◽  
K. Brelsford
2000 ◽  
Vol 610 ◽  
Author(s):  
G. Curello ◽  
R. Rengarajan ◽  
J. Faul ◽  
H. Wurzer ◽  
J. Amon ◽  
...  

AbstractIn this work, we report on the effect of different dual gate oxide (DGox) processes on the electrical properties of CMOS devices in deep submicron embedded DRAM (eDRAM) technology. Also discussed, is the effect of N+ Ion Implantation on the diffusion / segregation behaviour of B and In channel dopants. In particular, it will be shown that the N+ dose required to obtain a certain combination of dual gate oxide thickness varies with the gate oxide process. Effects of N+ dose on the In and B channel profiles are studied using SIMS. The impact of “thickness-equivalent” DGox processes on short channel effect (SCE) and carrier mobility is analyzed and tradeoffs for optimization of device performances are discussed.


1993 ◽  
Vol 306 ◽  
Author(s):  
L.K. Wang ◽  
A. Acovic ◽  
W.H. Chang

AbstractX-ray lithography introduces device radiation damage from the high energy photons during the lithography process. We have studied this effect on deep submicron n- and p-channel MOSFETs with gate dielectric thickness at 7 to 13 nm. After the x-ray irradiation the device characteristics are strongly affected by the generation of oxide charges, interface states and electron traps. These introduced damages cause the reduction of device transconductance, shift of the threshold voltages and increased leakage current. However, this degradation of device and circuit is lessened from technology scaling by thinning the gate oxide and lowering the supply voltage. The x-ray radiation damage, induces interface states and oxide charges which can be annealed out with a low temperature (400°C) forming gas (FG, 90% N2, 10% H2) annealing process. The device properties are essential unchanged after the annealing process. However, the residue damage is shown to enhance hot-carrier instability of p-channel devices if the remaining neutral traps act as electron or hole traps in the SiO2. In this paper, we investigate the radiation effects on the n- and p-channel MOSFETS fabricated with deep submicron device processes with thinner gate oxides and compare the hot carrier reliability of these devices after the synchrotron x-ray irradiation and also after the post metal forming gas annealing. The results indicate the device hot carrier instability has no effect on the devices with thin gate oxide with thickness approaching the electron tunneling range.


1996 ◽  
Vol 428 ◽  
Author(s):  
Abhijit Phanse ◽  
Samar Saha

AbstractThis paper addresses hot-carrier related reliability issues in deep submicron silicon nMOSFET devices. In order to monitor the hot-carrier induced device degradation, the substrate current was measured for devices with varying channel lengths (20 um - 0.24 um) under various biasing conditions. Deep submicron devices experience velocity saturation of channel carriers due to extremely high lateral electric fields. To evaluate the effects of velocity saturation in the channel, the pinch-off length in the channel was extracted for all the devices of the target technology. It was observed that for very short channel devices, carriers in most of the channel experience velocity saturation and almost the entire channel gets pinched off. It is shown in this paper that for very short channel devices, the pinch-off length in the channel is limited by the effective channel length, and that velocity saturation effects are critical to the transport of channel carriers.


1993 ◽  
Author(s):  
Eric S. Snyder ◽  
Ashish Kapoor ◽  
Clint Anderson
Keyword(s):  

2007 ◽  
Vol 101 (12) ◽  
pp. 124313 ◽  
Author(s):  
M. Yang ◽  
T. P. Chen ◽  
J. I. Wong ◽  
C. Y. Ng ◽  
Y. Liu ◽  
...  

1980 ◽  
Vol 1 ◽  
Author(s):  
T. O. Yep ◽  
R. T. Fulks ◽  
R. A. Powell

ABSTRACTSuccessful annealing of p+ n arrays fabricated by ion-implantation of 11B (50 keV, 1 × 1014 cm-2) into Si (100 has been performed using a broadly rastered, low-resolution (0.25-inch diameter) electron beam. A complete 2" wafer could be uniformly annealed in ≃20 sec with high electrical activation (>75%) and small dopant redistribution (≃450 Å). Annealing resulted In p+n junctions characterized by low reverse current (≃4 nAcm-2 at 5V reverse bias) and higher carrier lifetime (80 μsec) over the entire 2" wafer. Based on the electrical characteristics of the diodes, we estimate that the electron beam anneal was able to remove ion implantation damage and leave an ordered substrate to a depth of 5.5 m below the layer junction.


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