Through-the-gate-implanted ultrathin gate oxide MOSFET's with corner parasitics-free shallow-trench-isolation

1999 ◽  
Vol 20 (7) ◽  
pp. 363-365 ◽  
Author(s):  
U. Schwalke ◽  
A. Gschwandtner ◽  
G. Innertsberger ◽  
M. Kerber
Keyword(s):  
Gate Oxide ◽  
Shallow Trench Isolation ◽  
Trench Isolation

Gate-Prior-To-Isolation Cmos-Technology with Through-The-Gate-Implanted Ultra-Thin Gate Oxides

1999 ◽  
Vol 567 ◽  
Author(s):  
Udo Schwalke ◽  
Christian Gruensfelder ◽  
Alexander Gschwandtner ◽  
Gudrun Innertsberger ◽  
Martin Kerber
Keyword(s):  
Gate Oxide ◽  
Cmos Technology ◽  
Wafer Surface ◽  
Shallow Trench Isolation ◽  
Trench Isolation ◽  
Process Architecture ◽  
Process Complexity ◽  
Mos Gate ◽  
Cluster Tool

ABSTRACTWe have realized direct-tunneling gate oxide (1.6nm) NMOS and PMOS transistors by means of through-the-gate-implantation in a comer parasitics-free shallow-trench-isolation CMOS technology. In order to take full advantage of in-situ cluster-tool processing and to preserve initial wafer-surface quality, the essential part of the MOS gate is fabricated prior to device isolation and through-the-gate-implantation is utilized for well- and channel doping. In addition, a fully-reinforced-gate-oxide-perimeter is provided and trench comer parasitics are eliminated by the advanced process architecture EXTIGATE without increasing process complexity.

Dislocation-Free Shallow Trench Isolation (STI) Chemical Mechanical Polishing (CMP) Process for Embedded Flash Memory

2007 ◽  
Vol 124-126 ◽  
pp. 29-32
Author(s):  
Nam Hoon Kim ◽  
Hae Young Yoo ◽  
Eui Goo Chang
Keyword(s):  
Flash Memory ◽  
Chemical Mechanical Polishing ◽  
Gate Oxide ◽  
Mechanical Polishing ◽  
The Other ◽  
Shallow Trench Isolation ◽  
Trench Isolation ◽  
Dry Oxidation ◽  
The Impact ◽  
Embedded Flash

The ambient and denuded trench top corner at the step of gate oxidation play an important role to generate defect. Furthermore, dislocation-free flash process is proposed, and its mechanism as well. The impact on dislocation of the other processes is also discussed. And we knew that using of dry oxidation for gate oxide has the characteristic to reduce the dislocation. Consequently, the dislocation free wafer is obtained by changing gate oxide from wet to dry in manufacturing embedded flash.

A Closer “Look” at Modern Gate Oxides

2000 ◽  
Vol 611 ◽  
Author(s):  
Frieder H. Baumann ◽  
C.-P. Chang ◽  
John L. Grazul ◽  
Avid Kamgar ◽  
C. T. Liu ◽  
...  
Keyword(s):  
High Resolution ◽  
Oxidation Behavior ◽  
Gate Oxide ◽  
Interface Roughness ◽  
Si Substrate ◽  
Gate Oxides ◽  
Shallow Trench Isolation ◽  
Trench Isolation ◽  
High Resolution Tem ◽  
Image Simulations

ABSTRACTUsing high resolution TEM (HRTEM), we identified some process induced ‘weak spots’ in SiO2 layers: First, we observed thinning in the periphery of the transistor, i. e. near the boundary to the shallow trench isolation. At the boundary to the shallow trench, the Si substrate gradually changes its orientation from <100> to <110>, which results in an unexpected oxidation behavior in this region. Secondly, we observed the intrusion of poly-Si grains from the gate into the gate oxide, resulting in local thinning of the dielectric. Using image simulations, we show that conventional high resolution TEM can reveal the interface roughness only to a very limited extend.

Micro-Raman Spectroscopy Evaluation of the Local Mechanical Stress in Shallow Trench Isolation CMOS Structures: Correlation with Defect Generation and Diode Leakage

1998 ◽  
Author(s):  
I. De Wolf ◽  
G. Groeseneken ◽  
H.E. Maes ◽  
M. Bolt ◽  
K. Barla ◽  
...  
Keyword(s):  
Raman Spectroscopy ◽  
Mechanical Stress ◽  
Defect Formation ◽  
Active Area ◽  
Wet Oxidation ◽  
Leakage Currents ◽  
Shallow Trench Isolation ◽  
Micro Raman Spectroscopy ◽  
Silicon Devices ◽  
Trench Isolation

Abstract It is shown, using micro-Raman spectroscopy, that Shallow Trench Isolation introduces high stresses in the active area of silicon devices when wet oxidation steps are used. These stresses result in defect formation in the active area, leading to high diode leakage currents. The stress levels are highest near the outer edges of line structures and at square structures. They also increase with decreasing active area dimensions.

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