scholarly journals Converter-free multiple-voltage scaling techniques for low-power CMOS digital design

2001 ◽  
Vol 20 (1) ◽  
pp. 172-176 ◽  
Author(s):  
Yi-Jong Yeh ◽  
Sy-Yen Kuo ◽  
Jing-Yang Jou
Keyword(s):  
Low Power ◽  
Voltage Scaling ◽  
Digital Design ◽  
Low Power Cmos

scholarly journals AN OPTIMIZATION-BASED MULTIPLE-VOLTAGE SCALING TECHNIQUE FOR LOW-POWER CMOS DIGITAL DESIGN

2002 ◽  
Vol 11 (04) ◽  
pp. 365-375 ◽  
Author(s):  
YI-JONG YEH ◽  
SY-YEN KUO
Keyword(s):  
Low Power ◽  
Voltage Scaling ◽  
Path Selection ◽  
Digital Design ◽  
Selection Algorithm ◽  
Scaling Technique ◽  
Low Power Cmos ◽  
Optimal Values ◽  
Supply Voltages ◽  
Multiple Supply Voltages

In this paper, we propose a voltage scaling technique with multiple supply voltages for low-power designs. We adopt the path sensitization technique and release the clustering constraint used by the previous works. Our technique first operates the gates with the lowest feasible supply voltages and then uses an existing path selection algorithm for optimization. Experiments are conducted on all ISCAS85 benchmarks and the results show that significant power can be further reduced by our technique in comparison with the previous works. Furthermore, the results generated by our technique are close to the optimal values.

Supply and threshold voltage scaling for low power CMOS

1997 ◽  
Vol 32 (8) ◽  
pp. 1210-1216 ◽  
Author(s):  
R. Gonzalez ◽  
B.M. Gordon ◽  
M.A. Horowitz
Keyword(s):  
Low Power ◽  
Threshold Voltage ◽  
Voltage Scaling ◽  
Low Power Cmos

scholarly journals Low-power CMOS digital design

1992 ◽  
Vol 27 (4) ◽  
pp. 473-484 ◽  
Author(s):  
A.P. Chandrakasan ◽  
S. Sheng ◽  
R.W. Brodersen
Keyword(s):  
Low Power ◽  
Digital Design ◽  
Low Power Cmos

A simple voltage scaling formula for low-power CMOS circuits

1999 ◽  
Vol 46 (4) ◽  
pp. 803-805
Author(s):  
Dee-Gwan Kang ◽  
Young June Park ◽  
Hong Shick Min
Keyword(s):  
Low Power ◽  
Voltage Scaling ◽  
Cmos Circuits ◽  
Low Power Cmos
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