Low-power CMOS digital design with dual embedded adaptive power supplies

2000 ◽  
Vol 35 (4) ◽  
pp. 652-655 ◽  
Author(s):  
T. Kuroda ◽  
M. Hamada
Keyword(s):  
Low Power ◽  
Digital Design ◽  
Power Supplies ◽  
Low Power Cmos ◽  
Adaptive Power

scholarly journals Low-power CMOS digital design

1992 ◽  
Vol 27 (4) ◽  
pp. 473-484 ◽  
Author(s):  
A.P. Chandrakasan ◽  
S. Sheng ◽  
R.W. Brodersen
Keyword(s):  
Low Power ◽  
Digital Design ◽  
Low Power Cmos

scholarly journals AN OPTIMIZATION-BASED MULTIPLE-VOLTAGE SCALING TECHNIQUE FOR LOW-POWER CMOS DIGITAL DESIGN

2002 ◽  
Vol 11 (04) ◽  
pp. 365-375 ◽  
Author(s):  
YI-JONG YEH ◽  
SY-YEN KUO
Keyword(s):  
Low Power ◽  
Voltage Scaling ◽  
Path Selection ◽  
Digital Design ◽  
Selection Algorithm ◽  
Scaling Technique ◽  
Low Power Cmos ◽  
Optimal Values ◽  
Supply Voltages ◽  
Multiple Supply Voltages

In this paper, we propose a voltage scaling technique with multiple supply voltages for low-power designs. We adopt the path sensitization technique and release the clustering constraint used by the previous works. Our technique first operates the gates with the lowest feasible supply voltages and then uses an existing path selection algorithm for optimization. Experiments are conducted on all ISCAS85 benchmarks and the results show that significant power can be further reduced by our technique in comparison with the previous works. Furthermore, the results generated by our technique are close to the optimal values.

PVT ‐compensated low‐voltage and low‐power CMOS LNA for IoT applications

2020 ◽  
Vol 30 (11) ◽  
Author(s):  
Sajad Nejadhasan ◽  
Fatemeh Zaheri ◽  
Ebrahim Abiri ◽  
Mohammad Reza Salehi
Keyword(s):  
Low Power ◽  
Low Voltage ◽  
Iot Applications ◽  
Low Power Cmos ◽  
Cmos Lna
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