Transistor sizing for low power CMOS circuits

M. Borah; R.M. Owens; M.J. Irwin

doi:10.1109/43.503935

Transistor sizing for low power CMOS circuits

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ◽

10.1109/43.503935 ◽

1996 ◽

Vol 15 (6) ◽

pp. 665-671 ◽

Cited By ~ 41

Author(s):

M. Borah ◽

R.M. Owens ◽

M.J. Irwin

Keyword(s):

Low Power ◽

Cmos Circuits ◽

Transistor Sizing ◽

Low Power Cmos

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Transistor sizing and VDD scaling for low power CMOS circuits

2009 Joint IEEE North-East Workshop on Circuits and Systems and TAISA Conference ◽

10.1109/newcas.2009.5290468 ◽

2009 ◽

Cited By ~ 1

Author(s):

Adnan Kabbani

Keyword(s):

Low Power ◽

Cmos Circuits ◽

Transistor Sizing ◽

Low Power Cmos

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Dual-threshold voltage assignment with transistor sizing for low power CMOS circuits

IEEE Transactions on Very Large Scale Integration (VLSI) Systems ◽

10.1109/92.924061 ◽

2001 ◽

Vol 9 (2) ◽

pp. 390-394 ◽

Cited By ~ 55

Author(s):

P. Pant ◽

R.K. Roy ◽

A. Chattejee

Keyword(s):

Low Power ◽

Threshold Voltage ◽

Cmos Circuits ◽

Transistor Sizing ◽

Low Power Cmos ◽

Dual Threshold Voltage

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Dual-threshold voltage assignment with transistor sizing for low power CMOS circuits

42nd Midwest Symposium on Circuits and Systems (Cat. No.99CH36356) ◽

10.1109/mwscas.1999.867200 ◽

2003 ◽

Cited By ~ 1

Author(s):

P. Pant ◽

R.K. Roy ◽

A. Chatterjee

Keyword(s):

Low Power ◽

Threshold Voltage ◽

Cmos Circuits ◽

Transistor Sizing ◽

Low Power Cmos ◽

Dual Threshold Voltage

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32 nm high current performance double gate MOSFET for low power CMOS circuits

International Journal of Electronics ◽

10.1080/00207217.2014.896420 ◽

2014 ◽

Vol 102 (3) ◽

pp. 347-361

Author(s):

Morteza Rahimian ◽

Ali A. Orouji ◽

Amirhossein Aminbeidokhti

Keyword(s):

Low Power ◽

Cmos Circuits ◽

Double Gate ◽

High Current ◽

Double Gate Mosfet ◽

Low Power Cmos

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Compact modeling of power devices embedded in advanced low-power CMOS circuits

2016 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD) ◽

10.1109/sispad.2016.7605184 ◽

2016 ◽

Cited By ~ 1

Author(s):

Y. Hirano ◽

H. Kikuchihara ◽

T. Iizuka ◽

M. Miura-Mattausch ◽

H. J. Mattausch ◽

...

Keyword(s):

Low Power ◽

Compact Modeling ◽

Cmos Circuits ◽

Power Devices ◽

Low Power Cmos

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Synthesis of low-power CMOS circuits using hybrid topologies

Integration ◽

10.1016/s0167-9260(99)00004-8 ◽

1999 ◽

Vol 27 (2) ◽

pp. 143-163 ◽

Cited By ~ 2

Author(s):

Michael Gallant ◽

Dhamin Al-Khalili

Keyword(s):

Low Power ◽

Cmos Circuits ◽

Low Power Cmos

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High-performance low-power CMOS circuits using multiple channel length and multiple oxide thickness

Proceedings 2000 International Conference on Computer Design ◽

10.1109/iccd.2000.878290 ◽

2002 ◽

Cited By ~ 47

Author(s):

N. Sirisantana ◽

L. Wei ◽

K. Roy

Keyword(s):

Low Power ◽

High Performance ◽

Oxide Thickness ◽

Channel Length ◽

Cmos Circuits ◽

Multiple Channel ◽

Low Power Cmos

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Low-Power CMOS Circuits

10.1201/9781315220710 ◽

2018 ◽

Author(s):

Christian Piguet

Keyword(s):

Low Power ◽

Cmos Circuits ◽

Low Power Cmos

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Gate delay modeling for pre- and post-silicon timing related tasks for ultra-low power CMOS circuits

2013 IEEE 31st International Conference on Computer Design (ICCD) ◽

10.1109/iccd.2013.6657047 ◽

2013 ◽

Author(s):

Prasanjeet Das ◽

Sandeep K. Gupta

Keyword(s):

Low Power ◽

Cmos Circuits ◽

Gate Delay ◽

Ultra Low Power ◽

Low Power Cmos

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Low-power CMOS circuits for analog VLSI programmable neural networks

Proceedings of the 12th IEEE International Conference on Fuzzy Systems (Cat. No.03CH37442) ◽

10.1109/icm.2003.238250 ◽

2003 ◽

Cited By ~ 2

Author(s):

M.A.A. El-Soud ◽

R.A. AbdelRassoul ◽

H.H. Soliman ◽

L.M. El-Ghanam

Keyword(s):

Neural Networks ◽

Low Power ◽

Analog Vlsi ◽

Cmos Circuits ◽

Low Power Cmos

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