High-performance low-power CMOS circuits using multiple channel length and multiple oxide thickness

2002 ◽  
Author(s):  
N. Sirisantana ◽  
L. Wei ◽  
K. Roy
Keyword(s):  
Low Power ◽  
High Performance ◽  
Oxide Thickness ◽  
Channel Length ◽  
Cmos Circuits ◽  
Multiple Channel ◽  
Low Power Cmos

A low-voltage, low-power voltage reference based on subthreshold MOSFETs

2017 ◽  
Vol 31 (19-21) ◽  
pp. 1740069 ◽  
Author(s):  
Liangwei Dong ◽  
Yueli Hu
Keyword(s):  
Low Power ◽  
Temperature Coefficient ◽  
High Performance ◽  
Low Voltage ◽  
Supply Voltage ◽  
Channel Length ◽  
Voltage Reference ◽  
Single Chip ◽  
Low Power Cmos ◽  
Cmos Voltage Reference

A novel low-voltage low-power CMOS voltage reference independent of temperature is presented in this design. After considering the combined effect of (1) a perfect suppression of the temperature dependence of mobility; (2) the compensation of the channel length modulation effect on the temperature coefficient, a temperature coefficient of 10 ppm/[Formula: see text]C is achieved. Moreover, by adopting the subthreshold MOSFETs, there are no resistors used in the proposed structure. Therefore, the maximum supply current measured at the maximum supply voltage is 70 nA and at 80[Formula: see text]C. The circuit can be used as a voltage reference for high performance and low power dissipation on a single chip.

scholarly journals A HIGH-PERFORMANCE AND LOW-POWER DELAY BUFFER

2013 ◽  
pp. 78-82
Author(s):  
GOPALA KRISHNA.M ◽  
UMA SANKAR.CH ◽  
NEELIMA. S ◽  
KOTESWARA RAO.P
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
High Speed ◽  
High Performance ◽  
Vlsi Design ◽  
Flip Flop ◽  
Ring Counter ◽  
Double Edge ◽  
Low Power Cmos ◽  
Cmos Vlsi

In this paper, presents circuit design of a low-power delay buffer. The proposed delay buffer uses several new techniques to reduce its power consumption. Since delay buffers are accessed sequentially, it adopts a ring-counter addressing scheme. In the ring counter, double-edge-triggered (DET) flip-flops are utilized to reduce the operating frequency by half and the C-element gated-clock strategy is proposed. Both total transistor count and the number of clocked transistors are significantly reduced to improve power consumption and speed in the flip-flop. The number of transistors is reduced by 56%-60% and the Area-Speed-Power product is reduced by 56%-63% compared to other double edge triggered flip-flops. This design is suitable for high-speed, low-power CMOS VLSI design applications.

32 nm high current performance double gate MOSFET for low power CMOS circuits

2014 ◽  
Vol 102 (3) ◽  
pp. 347-361
Author(s):  
Morteza Rahimian ◽  
Ali A. Orouji ◽  
Amirhossein Aminbeidokhti
Keyword(s):  
Low Power ◽  
Cmos Circuits ◽  
Double Gate ◽  
High Current ◽  
Double Gate Mosfet ◽  
Low Power Cmos
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