Test set compaction for combinational circuits

Jau-Shien Chang;  Chen-Shang Lin

doi:10.1109/43.469663

Test set compaction for combinational circuits

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ◽

10.1109/43.469663 ◽

1995 ◽

Vol 14 (11) ◽

pp. 1370-1378 ◽

Cited By ~ 51

Author(s):

Jau-Shien Chang ◽

Chen-Shang Lin

Keyword(s):

Combinational Circuits ◽

Test Set ◽

Test Set Compaction

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Test set compaction procedure for combinational circuits based on decomposition tree

2011 9th East-West Design & Test Symposium (EWDTS) ◽

10.1109/ewdts.2011.6116596 ◽

2011 ◽

Cited By ~ 3

Author(s):

Valentina Andreeva

Keyword(s):

Combinational Circuits ◽

Decomposition Tree ◽

Test Set ◽

Test Set Compaction

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Test set compaction algorithms for combinational circuits

1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287) ◽

10.1145/288548.288615 ◽

1998 ◽

Cited By ~ 47

Author(s):

Ilker Hamzaoglu ◽

Janak H. Patel

Keyword(s):

Combinational Circuits ◽

Test Set ◽

Test Set Compaction

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Test set compaction for combinational circuits

Proceedings First Asian Test Symposium (ATS `92) ◽

10.1109/ats.1992.224429 ◽

2003 ◽

Cited By ~ 35

Author(s):

Jau-Shien Chang ◽

Chen-Shang Lin

Keyword(s):

Combinational Circuits ◽

Test Set ◽

Test Set Compaction

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A new approach for test set compaction in combinational circuits

2011 3rd International Conference on Electronics Computer Technology ◽

10.1109/icectech.2011.5941624 ◽

2011 ◽

Author(s):

S M. Thamarai ◽

K. Kuppusamy ◽

T. Meyyappan

Keyword(s):

Combinational Circuits ◽

Test Set ◽

New Approach ◽

Test Set Compaction

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Test set compaction algorithms for combinational circuits

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ◽

10.1109/43.856980 ◽

2000 ◽

Vol 19 (8) ◽

pp. 957-963 ◽

Cited By ~ 85

Author(s):

I. Hamzaoglu ◽

J.H. Patel

Keyword(s):

Combinational Circuits ◽

Test Set ◽

Test Set Compaction

Download Full-text

Test set compaction algorithms for combinational circuits

1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287) ◽

10.1109/iccad.1998.742885 ◽

2002 ◽

Cited By ~ 8

Author(s):

I. Hamzaoglu ◽

J.H. Patel

Keyword(s):

Combinational Circuits ◽

Test Set ◽

Test Set Compaction

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A research of heuristic optimization approaches to the test set compaction procedure based on a decomposition tree for combinational circuits

East-West Design & Test Symposium (EWDTS 2013) ◽

10.1109/ewdts.2013.6673219 ◽

2013 ◽

Author(s):

Valentina Andreeva ◽

Kirill A. Sorudeykin

Keyword(s):

Heuristic Optimization ◽

Combinational Circuits ◽

Decomposition Tree ◽

Test Set ◽

Test Set Compaction

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A fault avoidance approach with test set generation in combinational circuits using genetic algorithm

2018 2nd International Conference on Inventive Systems and Control (ICISC) ◽

10.1109/icisc.2018.8399045 ◽

2018 ◽

Cited By ~ 2

Author(s):

Namita Arya ◽

Amit Prakash Singh

Keyword(s):

Genetic Algorithm ◽

Combinational Circuits ◽

Test Set

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On low power test and DFT techniques for test set compaction

10.17077/etd.2bph30y6 ◽

2008 ◽

Author(s):

Santiago Remersaro

Keyword(s):

Low Power ◽

Test Set ◽

Power Test ◽

Low Power Test ◽

Test Set Compaction

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Application of Sequential Test Set Compaction to LFSR Reseeding

2008 NORCHIP ◽

10.1109/norchp.2008.4738292 ◽

2008 ◽

Cited By ~ 2

Author(s):

Igor Aleksejev ◽

Artur Jutman ◽

Jaan Raik ◽

Raimund Ubar

Keyword(s):

Sequential Test ◽

Test Set ◽

Lfsr Reseeding ◽

Test Set Compaction

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