East-West Design & Test Symposium (EWDTS 2013)
Latest Publications

TOTAL DOCUMENTS

146

(FIVE YEARS 0)

H-INDEX

(FIVE YEARS 0)

Published By IEEE

9781479920969, 9781479920952

Latest Documents Most Cited Documents Contributed Authors Related Sources Related Keywords

Malfunctions modeling of converters and homogeneous-chain distributed structure devices

East-West Design & Test Symposium (EWDTS 2013) ◽

10.1109/ewdts.2013.6673177 ◽

2013 ◽

Author(s):

Artur Gulin ◽

Zhanna Sukhinets

Keyword(s):

Distributed Structure

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Nonlinear filtering of pseudonoise signals using high-order Markov chain model

East-West Design & Test Symposium (EWDTS 2013) ◽

10.1109/ewdts.2013.6673137 ◽

2013 ◽

Cited By ~ 3

Author(s):

Dmitriy Prozorov ◽

Anton Chistyakov

Keyword(s):

Markov Chain ◽

Nonlinear Filtering ◽

Markov Chain Model ◽

High Order ◽

Chain Model ◽

Order Markov Chain

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Static analysis of HDL descriptions: Extracting models for verification

East-West Design & Test Symposium (EWDTS 2013) ◽

10.1109/ewdts.2013.6673126 ◽

2013 ◽

Cited By ~ 1

Author(s):

Alexander Kamkin ◽

Sergey Smolov ◽

Igor Melnichenko

Keyword(s):

Static Analysis

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Quantum models for description of digital systems

East-West Design & Test Symposium (EWDTS 2013) ◽

10.1109/ewdts.2013.6673086 ◽

2013 ◽

Author(s):

V.I. Hahanov ◽

I.V. Hahanova ◽

E.I. Litvinova ◽

S.V. Chumachenko ◽

A. Priymak ◽

...

Keyword(s):

Digital Systems ◽

Quantum Models

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Low-power design of combinational CMOS networks

East-West Design & Test Symposium (EWDTS 2013) ◽

10.1109/ewdts.2013.6673100 ◽

2013 ◽

Author(s):

Dmitry Cheremisinov ◽

Liudmila Cheremisinova

Keyword(s):

Low Power ◽

Low Power Design

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The hardware architecture and device for accurate time signal processing

East-West Design & Test Symposium (EWDTS 2013) ◽

10.1109/ewdts.2013.6673107 ◽

2013 ◽

Cited By ~ 3

Author(s):

Jiri Dostal ◽

Vladimir Smotlacha

Keyword(s):

Signal Processing ◽

Hardware Architecture ◽

Time Signal

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ASICPlacementAnalyzer: Software tool for data analysis and visualization of ASIC placement

East-West Design & Test Symposium (EWDTS 2013) ◽

10.1109/ewdts.2013.6673082 ◽

2013 ◽

Cited By ~ 2

Author(s):

Victor M. Kureichik ◽

Maria V. Lisyak

Keyword(s):

Data Analysis ◽

Software Tool

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Development of parameterized cell using Cadence Virtuoso

East-West Design & Test Symposium (EWDTS 2013) ◽

10.1109/ewdts.2013.6673156 ◽

2013 ◽

Cited By ~ 2

Author(s):

Vadim Borisov

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An efficient fault diagnosis and localization algorithm for Successive-Approximation Analog to Digital Converters

East-West Design & Test Symposium (EWDTS 2013) ◽

10.1109/ewdts.2013.6673194 ◽

2013 ◽

Author(s):

T. Melkumyan ◽

G. Harutyunyan ◽

S. Shoukourian ◽

V. Vardanian ◽

Y. Zorian

Keyword(s):

Fault Diagnosis ◽

Successive Approximation ◽

Analog To Digital Converters ◽

Localization Algorithm ◽

Analog To Digital

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East-West Design & Test Symposium (EWDTS 2013) ◽

10.1109/ewdts.2013.6673077 ◽

2013 ◽

Download Full-text

East-West Design & Test Symposium (EWDTS 2013)
Latest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE

Malfunctions modeling of converters and homogeneous-chain distributed structure devices

Nonlinear filtering of pseudonoise signals using high-order Markov chain model

Static analysis of HDL descriptions: Extracting models for verification

Quantum models for description of digital systems

Low-power design of combinational CMOS networks

The hardware architecture and device for accurate time signal processing

ASICPlacementAnalyzer: Software tool for data analysis and visualization of ASIC placement

Development of parameterized cell using Cadence Virtuoso

An efficient fault diagnosis and localization algorithm for Successive-Approximation Analog to Digital Converters

Contents

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East-West Design & Test Symposium (EWDTS 2013)Latest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE

Malfunctions modeling of converters and homogeneous-chain distributed structure devices

Nonlinear filtering of pseudonoise signals using high-order Markov chain model

Static analysis of HDL descriptions: Extracting models for verification

Quantum models for description of digital systems

Low-power design of combinational CMOS networks

The hardware architecture and device for accurate time signal processing

ASICPlacementAnalyzer: Software tool for data analysis and visualization of ASIC placement

Development of parameterized cell using Cadence Virtuoso

An efficient fault diagnosis and localization algorithm for Successive-Approximation Analog to Digital Converters

Contents

East-West Design & Test Symposium (EWDTS 2013)
Latest Publications