An all-analog multiphase delay-locked loop using a replica delay line for wide-range operation and low-jitter performance

2000 ◽  
Vol 35 (3) ◽  
pp. 377-384 ◽  
Author(s):  
Yongsam Moon ◽  
Jongsang Choi ◽  
Kyeongho Lee ◽  
Deog-Kyoon Jeong ◽  
Min-Kyu Kim
Keyword(s):  
Delay Line ◽  
Delay Locked Loop ◽  
Wide Range ◽  
Low Jitter

A wide range delay locked loop for low power and low jitter applications

2017 ◽  
Vol 46 (3) ◽  
pp. 401-414 ◽  
Author(s):  
Motahhareh Estebsari ◽  
Mohammad Gholami ◽  
Mohammad Javad Ghahramanpour
Keyword(s):  
Low Power ◽  
Delay Locked Loop ◽  
Wide Range ◽  
Low Jitter

A Wide-Range, Low-Power, All-Digital Delay-Locked Loop With Cyclic Half-Delay-Line Architecture

2015 ◽  
Vol 50 (11) ◽  
pp. 2635-2644 ◽  
Author(s):  
Jinn-Shyan Wang ◽  
Chun-Yuan Cheng ◽  
Pei-Yuan Chou ◽  
Tzu-Yi Yang
Keyword(s):  
Low Power ◽  
Delay Line ◽  
Delay Locked Loop ◽  
Wide Range

scholarly journals A Low-Jitter Harmonic-Free All-Digital Delay-Locked Loop for Multi-Channel Vernier TDC

Sensors ◽  
2021 ◽  
Vol 22 (1) ◽  
pp. 284
Author(s):  
Jiyun Tong ◽  
Sha Wang ◽  
Shuang Zhang ◽  
Mengdi Zhang ◽  
Ye Zhao ◽  
...  
Keyword(s):  
Closed Loop ◽  
Delay Line ◽  
Search Algorithm ◽  
Cmos Technology ◽  
Binary Search ◽  
Delay Lines ◽  
Delay Locked Loop ◽  
Binary Search Algorithm ◽  
Pvt Variations ◽  
Low Jitter

This paper presents a low jitter All-Digital Delay-Locked Loop (ADDLL) with fast lock time and process immunity. A coarse locking algorithm is proposed to prevent harmonic locking with just a small increase in hardware resources. In order to effectively solve the dithering phenomenon after locking, a replica delay line and a modified binary search algorithm with two modes were introduced in our ADDLL, which can significantly reduce the peak-to-peak jitter of the replica delay line. In addition, digital codes for a replica delay line can be conveniently applied to the delay line of multi-channel Vernier TDC while maintaining consistency between channels. The proposed ADDLL has been designed in 55 nm CMOS technology. In addition, the post-layout simulation results show that when operated at 1.2 V, the proposed ADDLL locks within 37 cycles and has a closed-loop characteristic, the peak-to-peak and root-mean-square jitter at 800 MHz are 6.5 ps and 1.18 ps, respectively. The active area is 0.024 mm2 and the power consumption at 800 MHz is 6.92 mW. In order to verify the performance of the proposed ADDLL, an architecture of dual ADDLL is applied to Vernier TDC to stabilize the Vernier delay lines against the process, voltage, and temperature (PVT) variations. With a 600 MHz operating frequency, the TDC achieves a 10.7 ps resolution, and the proposed ADDLL can keep the resolution stable even if PVT varies.

scholarly journals A Fast Lock All-Digital MDLL Using a Cyclic Vernier TDC for Burst-Mode Links

Electronics ◽  
2021 ◽  
Vol 10 (2) ◽  
pp. 177
Author(s):  
Dongjun Park ◽  
Sungwook Choi ◽  
Jongsun Kim
Keyword(s):  
Sampling Technique ◽  
Cmos Process ◽  
Detection Range ◽  
Delay Locked Loop ◽  
Delta Sigma Modulator ◽  
Correlated Double Sampling ◽  
Delta Sigma ◽  
Fast Power ◽  
Low Jitter ◽  
Reference Clock

An all-digital multiplying delay-locked loop (MDLL)-based clock multiplier featuring a time-to-digital converter (TDC) to achieve fast power-on capability is presented. The proposed MDLL adopts a new offset-free cyclic Vernier TDC to achieve a fast lock time of 15 reference clock cycles while maintaining a wide detection range and high resolution. The proposed offset-free TDC also uses a correlated double sampling technique to remove mismatch and offset issues, resulting in low jitter characteristics. After the MDLL is quickly locked, the TDC is turned off, and it goes into delta-sigma modulator (DSM)-based sequential tracking mode to reduce power consumption and improve jitter performance. Implemented in a 65-nm 1.0-V CMOS process, the proposed MDLL occupies an active area of 0.043 mm2 and generates a 2.4-GHz output clock from a 75-MHz reference clock (multiplication factor N = 32). It achieves an effective peak-to-peak jitter of 9.4 ps and consumes 3.3 mW at 2.4 GHz.

A wide-range delay-locked loop with a fixed latency of one clock cycle

2002 ◽  
Vol 37 (8) ◽  
pp. 1021-1027 ◽  
Author(s):  
Hsiang-Hui Chang ◽  
Jyh-Woei Lin ◽  
Ching-Yuan Yang ◽  
Shen-Iuan Liu
Keyword(s):  
Clock Cycle ◽  
Delay Locked Loop ◽  
Wide Range

Low Jitter and Wide Range VCO for CD/DVD/Blu-ray Disc

2006 ◽  
Author(s):  
Takashi Kawamoto ◽  
Masaru Kokubo ◽  
Shingi Kusakabe ◽  
Takehisa Yokohama
Keyword(s):  
Wide Range ◽  
Low Jitter
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