Low Jitter and Wide Range VCO for CD/DVD/Blu-ray Disc

2006 ◽  
Author(s):  
Takashi Kawamoto ◽  
Masaru Kokubo ◽  
Shingi Kusakabe ◽  
Takehisa Yokohama
Keyword(s):  
Wide Range ◽  
Low Jitter

A wide range delay locked loop for low power and low jitter applications

2017 ◽  
Vol 46 (3) ◽  
pp. 401-414 ◽  
Author(s):  
Motahhareh Estebsari ◽  
Mohammad Gholami ◽  
Mohammad Javad Ghahramanpour
Keyword(s):  
Low Power ◽  
Delay Locked Loop ◽  
Wide Range ◽  
Low Jitter

An all-analog multiphase delay-locked loop using a replica delay line for wide-range operation and low-jitter performance

2000 ◽  
Vol 35 (3) ◽  
pp. 377-384 ◽  
Author(s):  
Yongsam Moon ◽  
Jongsang Choi ◽  
Kyeongho Lee ◽  
Deog-Kyoon Jeong ◽  
Min-Kyu Kim
Keyword(s):  
Delay Line ◽  
Delay Locked Loop ◽  
Wide Range ◽  
Low Jitter

A low-jitter wide-range skew-calibrated dual-loop DLL using antifuse circuitry for high-speed DRAM

2002 ◽  
Vol 37 (6) ◽  
pp. 726-734 ◽  
Author(s):  
Se Jun Kim ◽  
Sang Hoon Hong ◽  
Jae-Kyung Wee ◽  
Joo Hwan Cho ◽  
Pil Soo Lee ◽  
...  
Keyword(s):  
High Speed ◽  
Wide Range ◽  
Low Jitter

Wide range-low jitter PLL design for serializer

2016 ◽  
Vol 23 (3) ◽  
pp. 583-591
Author(s):  
Jaydip K. Ravia ◽  
Mihir V. Shah ◽  
Harishanker Gupta ◽  
Sanjeev Mehta ◽  
Arup Roy Chowdhury
Keyword(s):  
Wide Range ◽  
Low Jitter

A low-jitter wide-range duty cycle corrector for high-speed high-precision ADC

2015 ◽  
Vol 46 (5) ◽  
pp. 333-342 ◽  
Author(s):  
Minjie Liu ◽  
Yingzi Jiang ◽  
Siwan Dong ◽  
Zhangming Zhu ◽  
Yintang Yang
Keyword(s):  
High Precision ◽  
Duty Cycle ◽  
High Speed ◽  
Wide Range ◽  
Low Jitter

A Wide Frequency Range Low Jitter Integer PLL with Switch and Inverter Based CP in 0.18 μm CMOS Technology

2019 ◽  
Vol 29 (09) ◽  
pp. 2050142
Author(s):  
Jagdeep Kaur Sahani ◽  
Anil Singh ◽  
Alpana Agarwal
Keyword(s):  
Phase Noise ◽  
Charge Pump ◽  
Cmos Technology ◽  
Wide Frequency Range ◽  
Phase Detector ◽  
Total Power ◽  
Control Voltage ◽  
Frequency Range ◽  
Wide Range ◽  
Low Jitter

This paper aims at designing a digital approach based low jitter, smaller area and wide frequency range phase locked loop (PLL) to reduce the design efforts and power which can be used in System-on-chip applications for operating frequency in the range of 0.025–1.6[Formula: see text]GHz. The low power, scalable and compact charge pump is proposed which reduces the overall power consumption and area of proposed PLL. A frequency phase detector (PFD) based on inverters and tri-state buffers have been proposed for the PLL. It is fast which improves the locking time of PLL. Also, pseudo-differential voltage controlled oscillator (VCO) is designed with CMOS inverter gates. The inverters are used as phase interpolator to maintain the phase difference of 180∘ between two outputs of VCO. Also, the inverters are used as variable capacitors to vary the frequency of proposed VCO with control voltage. It demonstrates the good phase noise performance enabling proposed PLL to have low jitter and wide frequency range. All the major blocks like PFD, charge pump and VCO are designed using digital gate methodology thus saving area and power and also reduce design efforts. Also, these digitally designed blocks enable the PLL to have low jitter small area and wide range. The proposed PLL is designed in a 0.18-[Formula: see text][Formula: see text]m CMOS technology with supply voltage of 1.8[Formula: see text]V. The output clocks with cycle-to-cycle jitter of 2.13[Formula: see text]ps at 1.6[Formula: see text]GHz. The phase noise of VCO is [Formula: see text]137[Formula: see text]dBc/Hz at an offset of 100[Formula: see text]MHz and total power consumed by the proposed PLL is 2.63[Formula: see text]mW at 1.6[Formula: see text]GHz.

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