Memory array architecture and decoding scheme for 3 V only sector erasable DINOR flash memory

1994 ◽  
Vol 29 (4) ◽  
pp. 454-460 ◽  
Author(s):  
S. Kobayashi ◽  
H. Nakai ◽  
Y. Kunori ◽  
T. Nakayama ◽  
Y. Miyawaki ◽  
...  
Keyword(s):  
Flash Memory ◽  
Memory Array ◽  
Array Architecture

scholarly journals Hardware-based Spiking Neural Network Using a TFT-Type AND Flash Memory Array Architecture Based on Direct Feedback Alignment

IEEE Access ◽  
2021 ◽  
pp. 1-1
Author(s):  
Won-Mook Kang ◽  
Dongseok Kwon ◽  
Sung Yun Woo ◽  
Soochang Lee ◽  
Honam Yoo ◽  
...  
Keyword(s):  
Neural Network ◽  
Flash Memory ◽  
Spiking Neural Network ◽  
Memory Array ◽  
Array Architecture ◽  
Direct Feedback

Novel Three Dimensional (3D) NAND Flash Memory Array Having Tied Bit-line and Ground Select Transistor (TiGer)

2012 ◽  
Vol E95.C (5) ◽  
pp. 837-841 ◽  
Author(s):  
Se Hwan PARK ◽  
Yoon KIM ◽  
Wandong KIM ◽  
Joo Yun SEO ◽  
Hyungjin KIM ◽  
...  
Keyword(s):  
Flash Memory ◽  
Three Dimensional ◽  
Nand Flash ◽  
Nand Flash Memory ◽  
Memory Array

Fitting Cells Into a Narrow $V_{T}$ Interval: Physical Constraints Along the Lifetime of an Extremely Scaled NAND Flash Memory Array

2015 ◽  
Vol 62 (5) ◽  
pp. 1491-1497 ◽  
Author(s):  
Giovanni Maria Paolucci ◽  
Christian Monzio Compagnoni ◽  
Alessandro S. Spinelli ◽  
Andrea L. Lacaita ◽  
Akira Goda
Keyword(s):  
Flash Memory ◽  
Nand Flash ◽  
Nand Flash Memory ◽  
Physical Constraints ◽  
Memory Array

Erratic Erase In ETOX/sup TM/ Flash Memory Array

1993 ◽  
Author(s):  
Ong ◽  
Fazio ◽  
Mielke ◽  
Pan ◽  
Righos ◽  
...  
Keyword(s):  
Flash Memory ◽  
Memory Array
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