Characterization of charge accumulation and detrapping processes related to latent failure in CMOS integrated circuits

1994 ◽  
Vol 30 (2) ◽  
pp. 350-357 ◽  
Author(s):  
W.D. Greason ◽  
K.W.K. Chum
Keyword(s):  
Integrated Circuits ◽  
Cmos Integrated Circuits ◽  
Charge Accumulation ◽  
Latent Failure

An SEM based system for a complete characterization of latch-up in CMOS integrated circuits

Scanning ◽  
1986 ◽  
Vol 8 (1) ◽  
pp. 20-33 ◽  
Author(s):  
C. Canali ◽  
F. Fantini ◽  
M. Giannini ◽  
A. Senin ◽  
M. Vanzi ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Complete Characterization ◽  
Cmos Integrated Circuits ◽  
Latch Up

Some applications of electron beam microanalysis techniques in VLSI process evaluation

1983 ◽  
Vol 41 ◽  
pp. 160-161
Author(s):  
Simon Thomas
Keyword(s):  
Integrated Circuits ◽  
Process Evaluation ◽  
Large Scale ◽  
Technology Development ◽  
Analytical Techniques ◽  
Successful Implementation ◽  
Analysis Of Failures ◽  
Characterization Of Materials ◽  
Circuits Vlsi

Trends in the technology development of very large scale integrated circuits (VLSI) have been in the direction of higher density of components with smaller dimensions. The scaling down of device dimensions has been not only laterally but also in depth. Such efforts in miniaturization bring with them new developments in materials and processing. Successful implementation of these efforts is, to a large extent, dependent on the proper understanding of the material properties, process technologies and reliability issues, through adequate analytical studies. The analytical instrumentation technology has, fortunately, kept pace with the basic requirements of devices with lateral dimensions in the micron/ submicron range and depths of the order of nonometers. Often, newer analytical techniques have emerged or the more conventional techniques have been adapted to meet the more stringent requirements. As such, a variety of analytical techniques are available today to aid an analyst in the efforts of VLSI process evaluation. Generally such analytical efforts are divided into the characterization of materials, evaluation of processing steps and the analysis of failures.

TEM characterization of WSix films

1994 ◽  
Vol 52 ◽  
pp. 848-849
Author(s):  
V. C. Kannan ◽  
S. M. Merchant ◽  
R. B. Irwin ◽  
A. K. Nanda ◽  
M. Sundahl ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Vapor Deposition ◽  
High Purity ◽  
Physical Vapor Deposition ◽  
Thermal Treatments ◽  
Rapid Thermal Anneal ◽  
Tungsten Silicide ◽  
Tem Characterization ◽  
Metal Silicides

Metal silicides such as WSi2, MoSi2, TiSi2, TaSi2 and CoSi2 have received wide attention in recent years for semiconductor applications in integrated circuits. In this study, we describe the microstructures of WSix films deposited on SiO2 (oxide) and polysilicon (poly) surfaces on Si wafers afterdeposition and rapid thermal anneal (RTA) at several temperatures. The stoichiometry of WSix films was confirmed by Rutherford Backscattering Spectroscopy (RBS). A correlation between the observed microstructure and measured sheet resistance of the films was also obtained.WSix films were deposited by physical vapor deposition (PVD) using magnetron sputteringin a Varian 3180. A high purity tungsten silicide target with a Si:W ratio of 2.85 was used. Films deposited on oxide or poly substrates gave rise to a Si:W ratio of 2.65 as observed by RBS. To simulatethe thermal treatments of subsequent processing procedures, wafers with tungsten silicide films were subjected to RTA (AG Associates Heatpulse 4108) in a N2 ambient for 60 seconds at temperatures ranging from 700° to 1000°C.

Detection and Characterization of an Electrical Failure Induced during Laser Ablation of Packages

2008 ◽  
Author(s):  
P. Schwindenhammer ◽  
H. Murray ◽  
P. Descamps ◽  
P. Poirier
Keyword(s):  
Laser Ablation ◽  
Integrated Circuits ◽  
Failure Analysis ◽  
Ablation Process ◽  
Thermally Induced ◽  
Electrical Failure ◽  
Electrical Phenomenon ◽  
Semiconductor Packages ◽  
Complex Semiconductor

Abstract Decapsulation of complex semiconductor packages for failure analysis is enhanced by laser ablation. If lasers are potentially dangerous for Integrated Circuits (IC) surface they also generate a thermal elevation of the package during the ablation process. During measurement of this temperature it was observed another and unexpected electrical phenomenon in the IC induced by laser. It is demonstrated that this new phenomenon is not thermally induced and occurs under certain ablation conditions.

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