DETECTION OF POTENTIALLY UNRELIABLE VLSI BASED ON THE ANALYSIS OF TEMPERATURE-SENSITIVE PARAMETERS

The paper discusses methods for non-destructive diagnostic testing of very large scale integration circuits (VLSI) based on the “junction-case” thermal resistance parameter. This parameter is important because VLSI’s failure rate depends on junction temperature, which in turn depends on thermal resistance “junction-case”. There are three known methods for detecting potentially unreliable VLSIs with increased thermal resistance value: 1) non-destructive measurement of thermal resistance; 2) scanning acoustic microscopy; 3) an approach based on the statistical analysis of temperature-sensitive electric parameters. The paper presents advantages and disadvantages of each method. Special attention is paid to statistical analysis of temperature-sensitive electric parameters because this method allows detecting of potentially unreliable VLSIs without using expensive equipment. This method does not require changes in existing measurement programs. Electric parameters, which depend on temperature, are temperature-sensitive parameters. These parameters are useful for detecting VLSIs with deviations from the main batch. This allows decreasing of risk of potentially unreliable VLSIs application in high reliable equipment. With the proposed approach the high reliable equipment lifetime can be increased.

Evaluating the Reliability Testing Acceleration Factor Based on VLSI Chip Infrared Image Analysis

A new approach for evaluating the acceleration factor of forced reliability tests of very large scale integrated circuits (VLSI) is presented. The approach is based on subjecting the VLSI chip to an infrared image analysis. Currently, the VLSI reliability testing acceleration factor is evaluated based on the Arrhenius law, according to which this factor depends on the chip temperature. The chip temperature, in turn, is represented by the sum of the chip package temperature and the product of the maximum dissipated power and the chip-to-package thermal resistance. The drawback of the existing method is that the calculation is carried out for only a single chip temperature value that was obtained analytically. But the VLSI is a complex system, and it is not correct to judge about the testing acceleration factor proceeding from a single chip temperature value. It is proposed to calculate the VLSI reliability testing acceleration factor based on the temperatures at many points on the VLSI chip surface. This will make it possible to take into account the test sequence influence on the temperature distribution over the chip surface, thereby helping select the test sequences so that to obtain the maximal and uniform chip heating. Owing to the proposed method, it becomes possible to evaluate the testing acceleration factor more accurately and also to potentially increase it by choosing the test sequence. A more accurate evaluation of the acceleration factor allows the reliability tests reliability to be improved. The proposed method for evaluating the acceleration factor was validated experimentally. The workplace is described, the calculations of the reliability testing acceleration factors using two approaches are carried out, and their comparison is given.

НИИ молекулярной электроники. Более полувека на переднем крае отечественной микроэлектроники

В научно-исследовательском институте молекулярной электроники уже более полувека успешно разрабатывают и внедряют в производство самые передовые в нашей стране технологии, интегральные схемы, СБИС, смарт-карты, радиационно-стойкие микросхемы для космоса, радиочастотные метки и чипы для паспортно-визовых документов со средствами криптографической защиты информации. Полностью готовы к внедрению оригинальные удостоверения личности гражданина РФ, новые микросхемы для платежной системы "МИР", созданные совместно с ПАО "Микрон", накоплен богатый опыт взаимодействия с Национальной системой платежных карт. Уникальность разработок института состоит и в создании встроенного ПО для микросхем радиочастотной идентификации. Стартовал совместный проект с МТС о разработке модулей безопасности для шифрования данных, передаваемых по радиочастотным каналам для Интернета вещей. Об этих и многих других достижениях НИИМЭ рассказывает первый заместитель генерального директора НИИМЭ Николай Алексеевич Шелепин. For more than half a century, the Molecular Electronics Research Institute has been successfully developing and implementing the most advanced technologies in our country, integrated circuits, VLSI, smart cards, radiation-resistant microcircuits for outer space, radio frequency tags and chips for passport and visa documents with cryptographic protection of information. The original identity cards of a citizen of the Russian Federation are fully ready for implementation, new microcircuits for the MIR payment system, created jointly with PJSC "Mikron", have accumulated rich experience of interaction with the National Payment Card System. The uniqueness of the Institute’s developments lies in the creation of embedded software for RFID microcircuits. A joint project with MTS has started on the development of security modules for encrypting data transmitted over radio frequency channels for the Internet of Things. Nikolay Alekseevich Shelepin, Deputy Director General of NIIME, talks about these and many other achievements of MERI.

Designing dual-chirality and multi-Vt repeaters for performance optimization of 32 nm interconnects

Purpose This paper is an unprecedented effort to resolve the performance issue of very large scale integrated circuits (VLSI) interconnects encountered because of the scaling of device dimensions. Repeater interpolation technique is an effective approach for enhancing speed of interconnect network. Proposed buffers as repeater are modeled by using dual chirality multi-Vt technology to reduce delay besides mitigating average power consumption. Interconnects modeled with carbon nanotube (CNT) technology are compared with copper interconnect for various lengths. Buffer circuits are designed with both CNT and metal oxide semiconductor technology for comparison by using various combination of (CMOSFET repeater-Cu interconnect) and (CNTFET repeater-CNT interconnect). Compared to conventional buffer, ProposedBuffer1 saves dynamic power by 84.86%, leakage power by 88% and offers reduction in delay by 72%. ProposedBuffer2 brings about dynamic power saving of 99.94%, leakage power saving of 93%, but causes delay penalty. Simulation using Stanford SPICE model for CNT and silicon-field effective transistor berkeley short-channel IGFET Model4 (BSIM4) predictive technology model (PTM) for MOS is done in H simulation program with integrated circuit emphasis for 32 nm. Design/methodology/approach Usually, the dynamic power consumption dominates the total power, while the leakage power has a negligible effect. But with the scaling of device technology, leakage power has become one of the important factors of consideration in low power design techniques. Various strategies are explored to suppress the leakage power in standby mode. The adoption of a multi-threshold design strategy is an effective approach to improve the performance of buffer circuits without compromising on the delay and area overhead. Unlike MOS technology, to implement multi-Vt transistors in case of CNT technology is quite easy. It can be achieved by varying diameter of carbon nanotubes using chirality control. Findings An unprecedented approach is taken for optimizing the delay and power dissipation and hence drastically reducing energy consumption by keeping proper harmony between wire technology and repeater-buffer technology. This paper proposes two novel ultra-low power buffers (PB1 and PB2) as repeaters for high-speed interconnect applications in portable devices. PB1 buffer implemented with high-speed CML technique nested with multi-threshold (Vt) technology sleep transistor so as to improve the speed along with a reduction in standby power consumption. PB2 is judicially implemented by inserting separable sized, dual chirality P type carbon nanotube field effective transistors. The HSpice simulation results justify the correctness of schemes. Originality/value Result analysis points out that compared to conventional Cu interconnect, the CNT interconnects paired with Proposed CNTFET buffer designs are more energy efficient. PB1 saves dynamic power by 84.86%, reduces propagation delay by 72% and leakage power consumption by 88%. PB2 brings about dynamic power saving of 99.4%, leakage power saving of 93%, with improvement in speed by 52%. This is mainly because of the fact that CNT interconnect offers low resistance and CNTFET drivers have high mobility and ballistic mode of operation.

Impact of Variation of Device Parameters on the Electrical Characteristics of Double-Gate Mosfets

Very large scale integrated circuits (VLSI) have been possible owing to the shrinking of metal-oxide semiconductor field-effect transistors (MOSFETs). By reducing the dimensions of the device it is possible to have high density on the chip. This increases the number of logical functions that can be implemented on a given dimension of the chip. Along with the advantages associated with the shrinking of the devices, it also has certain drawbacks commonly known as short-channel effects. Due to these effects, device characteristics deviate from its expected values. There are many techniques through which these deviations can be minimized. One of the promising and highly researched techniques these days is the use of Multi-gate (MG) transistors in VLSI. Double-gate (DG) transistor is one among MG transistors. In DG MOSFET, substrate is surrounded by gates from two opposite sides. This leads to more control over the channel electrons by the gate terminals. In this paper, the consequence of change of various device constraints on the electrical characteristics of the DG MOSFETs will be investigated. Through the results, one can know to what extent the electrical properties changes when the dimensions and/or material properties are changed. This will be very helpful in determining the maximum current associated with those dimensions of DG MOSFETs.

High-Speed Low-Power Bulk-Controlled Sense-Amplifier D Flip-Flop

With the development of digital very large scale integrated circuits (VLSI), how to reduce the power dissipation and improve the operation speed are two aspects among the most concerned fields. Based on sense amplifier technology and bulk-controlled technique, this paper proposes a bulk-controlled sense-amplifier D flip-flop (BCSADFF). Firstly, this flip-flop can change the threshold voltage of the NMOS by inputting control signals from the substrate so as to control the operating current. Secondly, the traditional RS flip-flop composed of two NAND gates is improved to a couple of inverters based on pseudo-PMOS dynamic technology. Therefore, the proposed BCSADFF can both effectively reduce the power dissipation and improve the circuit speed. Thirdly, the designed BCSADFF can work normally with ultra-dynamic voltage scaling from 1.8 V to 0.6V for SMIC 0.18-um standard CMOS process. Lastly, the Hspice simulation result shows that, compared with the traditional sense-amplifier D flip-flop (SADFF), the power dissipation of the BCSADFF is significantly reduced under the same operating conditions. When the power supply voltage is 0.9V, the power dissipation and delay of the SADFF is 6.54uW and 0.386ns while that of the proposed BCSADFF is 2.09uW and 0.237ns.

Microscale sensors based on silicon carbide and silicon

The current paper consists of two topics related to microelectromechanical systems (MEMS). The first topic reviews recent advances made in the area of silicon carbide (SiC) MEMS for applications in harsh environments. Given the unique properties of SiC, the potential and progress in the development and deployment of the harsh environment material for the fabrication and characterization of resonators and pressure sensors are described. The second topic details the motivation behind the study of biologically inspired systems and how silicon-based microscale sensors with out-of-plane structures could be integrated with analogue very-large-scale integrated circuits (VLSI) for insect-inspired robotic studies.