New aspects and mechanism of kink effect in static back-gate transconductance characteristics in fully-depleted SOI MOSFETs on high-dose SIMOX wafers

T. Ushiki; K. Kotani; T. Funaki; K. Kawai; T. Ohmi

doi:10.1109/16.822281

New aspects and mechanism of kink effect in static back-gate transconductance characteristics in fully-depleted SOI MOSFETs on high-dose SIMOX wafers

IEEE Transactions on Electron Devices ◽

10.1109/16.822281 ◽

2000 ◽

Vol 47 (2) ◽

pp. 360-366 ◽

Cited By ~ 9

Author(s):

T. Ushiki ◽

K. Kotani ◽

T. Funaki ◽

K. Kawai ◽

T. Ohmi

Keyword(s):

High Dose ◽

Back Gate ◽

Fully Depleted ◽

Kink Effect

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Back gate engineering for suppression of threshold voltage fluctuation in fully-depleted SOI MOSFETs

2000 IEEE International SOI Conference. Proceedings (Cat. No.00CH37125) ◽

10.1109/soi.2000.892778 ◽

2002 ◽

Author(s):

T. Numata ◽

M. Noguchi ◽

Y. Oowaki ◽

S. Takagi

Keyword(s):

Threshold Voltage ◽

Voltage Fluctuation ◽

Back Gate ◽

Fully Depleted ◽

Gate Engineering

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Analytical Subthreshold Current and Subthreshold Swing Models for a Fully Depleted (FD) Recessed-Source/Drain (Re-S/D) SOI MOSFET with Back-Gate Control

Journal of Electronic Materials ◽

10.1007/s11664-017-5508-7 ◽

2017 ◽

Vol 46 (8) ◽

pp. 5046-5056

Author(s):

Gopi Krishna Saramekala ◽

Pramod Kumar Tiwari

Keyword(s):

Subthreshold Swing ◽

Back Gate ◽

Fully Depleted ◽

Soi Mosfet ◽

Subthreshold Current ◽

Gate Control

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Elimination of kink effect in fully depleted complementary buried-channel SOL MOSFET (FD CBCMOS) based on silicon direct bonding technology

IEEE Electron Device Letters ◽

10.1109/55.75725 ◽

1991 ◽

Vol 12 (3) ◽

pp. 101-103 ◽

Cited By ~ 6

Author(s):

Qin-Yi Tong ◽

Xiao-Li Xu ◽

Hui-Zhen Zhang

Keyword(s):

Fully Depleted ◽

Buried Channel ◽

Kink Effect ◽

Bonding Technology

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Three-dimensional analytic modelling of front and back gate threshold voltages for small geometry fully depleted SOI MOSFET’s

Solid-State Electronics ◽

10.1016/j.sse.2011.03.009 ◽

2011 ◽

Vol 62 (1) ◽

pp. 174-184 ◽

Cited By ~ 6

Author(s):

Krishna Meel ◽

R. Gopal ◽

Deepak Bhatnagar

Keyword(s):

Three Dimensional ◽

Back Gate ◽

Fully Depleted ◽

Threshold Voltages

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A simple analytical model for the front and back gate threshold voltages of a fully-depleted asymmetric SOI MOSFET

Solid-State Electronics ◽

10.1016/j.sse.2008.05.014 ◽

2008 ◽

Vol 52 (8) ◽

pp. 1249-1255 ◽

Cited By ~ 8

Author(s):

Chung Ha Suh

Keyword(s):

Analytical Model ◽

Simple Analytical Model ◽

Back Gate ◽

Fully Depleted ◽

Soi Mosfet ◽

Threshold Voltages

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LDD and Back-Gate Engineering for Fully Depleted Planar SOI Transistors with Thin Buried Oxide

IEEE Transactions on Electron Devices ◽

10.1109/ted.2010.2046097 ◽

2010 ◽

Vol 57 (6) ◽

pp. 1319-1326 ◽

Cited By ~ 14

Author(s):

Ran Yan ◽

Russell Duane ◽

Pedram Razavi ◽

Aryan Afzalian ◽

Isabelle Ferain ◽

...

Keyword(s):

Back Gate ◽

Fully Depleted ◽

Buried Oxide ◽

Gate Engineering

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An Analytical Threshold Voltage Model of Fully Depleted (FD) Recessed-Source/Drain (Re-S/D) SOI MOSFETs with Back-Gate Control

Journal of Electronic Materials ◽

10.1007/s11664-016-4752-6 ◽

2016 ◽

Vol 45 (10) ◽

pp. 5367-5374 ◽

Cited By ~ 2

Author(s):

Gopi Krishna Saramekala ◽

Pramod Kumar Tiwari

Keyword(s):

Threshold Voltage ◽

Back Gate ◽

Fully Depleted ◽

Gate Control ◽

Threshold Voltage Model

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Threshold voltage sensitivity of 0.1 μm channel length fully-depleted SOI NMOSFET's with back-gate bias

IEEE Transactions on Electron Devices ◽

10.1109/16.405292 ◽

1995 ◽

Vol 42 (9) ◽

pp. 1707-1709 ◽

Cited By ~ 4

Author(s):

E. Leobandung ◽

S.Y. Chou

Keyword(s):

Threshold Voltage ◽

Channel Length ◽

Voltage Sensitivity ◽

Gate Bias ◽

Back Gate ◽

Fully Depleted

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Back-gate induced random telegraph signal noise in fully-depleted silicon-on-insulator nMOSFETs

Solid-State Electronics ◽

10.1016/0038-1101(93)90032-l ◽

1993 ◽

Vol 36 (11) ◽

pp. 1593-1596 ◽

Cited By ~ 4

Author(s):

E. Simoen ◽

U. Magnusson ◽

J. Vermeiren ◽

C. Claeys

Keyword(s):

Silicon On Insulator ◽

Back Gate ◽

Random Telegraph Signal ◽

Fully Depleted ◽

Signal Noise

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Back gate voltage and buried-oxide thickness influences on the series resistance of fully depleted SOI MOSFETs at 77 K

Journal de Physique IV (Proceedings) ◽

10.1051/jp4:1998306 ◽

1998 ◽

Vol 08 (PR3) ◽

pp. Pr3-25-Pr3-28

Author(s):

A. S. Nicolett ◽

J. A. Martino ◽

E. Simoen ◽

C. Claeys

Keyword(s):

Gate Voltage ◽

Series Resistance ◽

Oxide Thickness ◽

Back Gate ◽

Fully Depleted ◽

Buried Oxide

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