Back gate voltage and buried-oxide thickness influences on the series resistance of fully depleted SOI MOSFETs at 77 K

1998 ◽  
Vol 08 (PR3) ◽  
pp. Pr3-25-Pr3-28
Author(s):  
A. S. Nicolett ◽  
J. A. Martino ◽  
E. Simoen ◽  
C. Claeys
Keyword(s):  
Gate Voltage ◽  
Series Resistance ◽  
Oxide Thickness ◽  
Back Gate ◽  
Fully Depleted ◽  
Buried Oxide

LDD and Back-Gate Engineering for Fully Depleted Planar SOI Transistors with Thin Buried Oxide

2010 ◽  
Vol 57 (6) ◽  
pp. 1319-1326 ◽  
Author(s):  
Ran Yan ◽  
Russell Duane ◽  
Pedram Razavi ◽  
Aryan Afzalian ◽  
Isabelle Ferain ◽  
...  
Keyword(s):  
Back Gate ◽  
Fully Depleted ◽  
Buried Oxide ◽  
Gate Engineering

Towards High-Voltage MOSFETs in Ultrathin FDSOI

2016 ◽  
Vol 25 (01n02) ◽  
pp. 1640005 ◽  
Author(s):  
Antoine Litty ◽  
Sylvie Ortolland ◽  
Dominique Golanski ◽  
Christian Dutto ◽  
Alexandres Dartigues ◽  
...  
Keyword(s):  
High Voltage ◽  
Low Voltage ◽  
Ground Plane ◽  
Silicon Film ◽  
Silicon On Insulator ◽  
Drift Region ◽  
Back Gate ◽  
Fully Depleted ◽  
Buried Oxide ◽  
Core Technology

High-Voltage MOSFETs are essential devices for complementing and extending the domains of application of any core technology including low-power, low-voltage CMOS. In this paper, we propose and describe advanced Extended-Drain MOSFETs, designed, processed and characterized in ultrathin body and buried oxide Fully Depleted Silicon on Insulator technology (UTBB-FDSOI). These transistors have been implemented in two technology nodes (28 nm and 14 nm) with different silicon film and buried oxide thicknesses (TSi < 10nm and TBOX ≤ 25nm). Our innovative concept of Dual Ground Plane (DGP) provides RESURF-like effect (reduced surface field) and offers additional flexibility for HVMOS integration directly in the ultrathin film of the FDSOI wafer. In this configuration, the primary back-gate controls the threshold voltage (VTH) to ensure performance and low leakage current. The second back-gate, located underneath the drift region, acts as a field plate enabling the improvement of the ON resistance (RON) and breakdown voltage (BV). The trade-off RON.S versus BV is investigated as a function of doping level, length and thickness of the drift region. We report promising results and discuss further developments for successful integration of high-voltage MOSFETs in ultrathin CMOS FDSOI technology.

scholarly journals Parasitic Conduction Response to X-ray Radiation in Unstrained and Strained Triple-Gate SOI MuGFETs

2014 ◽  
Vol 9 (2) ◽  
pp. 97-102
Author(s):  
Fernando F. Teixeira ◽  
Caio C. M. Bordallo ◽  
Marcilei A. Guazzelli ◽  
Paula Ghedini Der Agopian ◽  
João Antonio Martino ◽  
...  
Keyword(s):  
Threshold Voltage ◽  
Gate Voltage ◽  
Drain Current ◽  
X Rays ◽  
Back Gate ◽  
X Ray ◽  
Dose Rates ◽  
Buried Oxide ◽  
Opposite Trend

In this work, the X-ray irradiation impact on the back gate conduction and drain current for Triple-Gate SOI FinFETs is investigated for strained and unstrained devices. Both types (P and N) of transistors were analyzed. Since X-rays promote trapped positive charges in the buried oxide, the second interface threshold voltage shifts to lower gate voltage. The performance of n-channel devices presented a strong degradation when submitted to X-rays, while for p-channel devices the opposite trend was observed. Two different dose rates were analyzed.

scholarly journals Parameters Extraction from C-V Curves in Triple-Gate FinFET

2008 ◽  
Vol 3 (2) ◽  
pp. 77-81
Author(s):  
Michele Rodrigues ◽  
Victor Sonnenberg ◽  
João Antonio Martino
Keyword(s):  
Numerical Simulations ◽  
Gate Voltage ◽  
Doping Concentration ◽  
Experimental Validation ◽  
Three Dimensional ◽  
Oxide Thickness ◽  
Experimental Measurements ◽  
Back Gate ◽  
Parameters Extraction

Methods to determine the effective oxide thickness (EOT), fin height (Hfin) and fin doping concentration (Nfin) through gate to drain/source capacitance as a function of the front and the back gate voltage curves in triple-gate nMOS FinFET are presented. The proposed methods were validated through three-dimensional numerical simulations and experimental measurements showing that these methods can be also applied in triple-gate nMOS FinFET devices as a powerful tool for experimental validation.

scholarly journals One Transistor Floating Body RAM Performances on UTBOX Devices Using the BJT Effect

2012 ◽  
Vol 7 (2) ◽  
pp. 113-120
Author(s):  
Luciano M. Almeida ◽  
Katia R. A. Sasaki ◽  
M. Aoulaiche ◽  
Eddy Simoen ◽  
Cor Clayes ◽  
...  
Keyword(s):  
Retention Time ◽  
Silicon Film ◽  
Random Access ◽  
Oxide Thickness ◽  
Silicon On Insulator ◽  
Floating Body ◽  
Fully Depleted ◽  
Buried Oxide ◽  
Drain Bias ◽  
Time Decrease

This work aims to analyze through 2D numerical simulations the minimum drain bias for the onset of the parasitic bipolar transistor (BJT) effect (VLatch) of a Ultra-Thin-Buried-Oxide (UTBOX) Fully-Depleted-Silicon-on-Insulator (FDSOI) transistor used as a Single-Transistor-Dynamic-Random-Access-Memory (1TDRAM) cell at high temperatures. The buried oxide thickness (tBOX) and silicon film thickness (tSi) variation were also taken into account and initial studies of the retention time (RT) and the data degradation have been performed. It was verified that the latch voltage, the sense margin current, the latch time and the retention time decrease as the temperature rises.

Behavior of contact-silicided TFSOI gate structures

1994 ◽  
Vol 52 ◽  
pp. 860-861
Author(s):  
N. David Theodore ◽  
Juergen Foerstner ◽  
Peter Fejes
Keyword(s):  
Semiconductor Device ◽  
Series Resistance ◽  
Field Effect Transistors ◽  
Silicon Layer ◽  
Device Fabrication ◽  
Silicon On Insulator ◽  
Continuous Layer ◽  
Buried Oxide ◽  
Device Structures ◽  
Thin Silicon

As semiconductor device dimensions shrink and packing-densities rise, issues of parasitic capacitance and circuit speed become increasingly important. The use of thin-film silicon-on-insulator (TFSOI) substrates for device fabrication is being explored in order to increase switching speeds. One version of TFSOI being explored for device fabrication is SIMOX (Silicon-separation by Implanted OXygen).A buried oxide layer is created by highdose oxygen implantation into silicon wafers followed by annealing to cause coalescence of oxide regions into a continuous layer. A thin silicon layer remains above the buried oxide (~220 nm Si after additional thinning). Device structures can now be fabricated upon this thin silicon layer.Current fabrication of metal-oxidesemiconductor field-effect transistors (MOSFETs) requires formation of a polysilicon/oxide gate between source and drain regions. Contact to the source/drain and gate regions is typically made by use of TiSi2 layers followedby Al(Cu) metal lines. TiSi2 has a relatively low contact resistance and reduces the series resistance of both source/drain as well as gate regions

scholarly journals Simulation of FDSOI-ISFET with Tunable Sensitivity by Temperature and Dual-Gate Structure

Electronics ◽  
2021 ◽  
Vol 10 (13) ◽  
pp. 1585
Author(s):  
Hanbin Wang ◽  
Jinshun Bi ◽  
Mengxin Liu ◽  
Tingting Han
Keyword(s):  
Gate Voltage ◽  
Computer Aided Design ◽  
Silicon On Insulator ◽  
Fully Depleted ◽  
Gate Structure ◽  
Different Temperatures ◽  
Dual Gate ◽  
Sensitivity Changes ◽  
Increasing Temperature ◽  
Aided Design

This work investigates the different sensitivities of an ion-sensitive field-effect transistor (ISFET) based on fully depleted silicon-on-insulator (FDSOI). Using computer-aided design (TCAD) tools, the sensitivity of a single-gate FDSOI based ISFET (FDSOI-ISFET) at different temperatures and the effects of the planar dual-gate structure on the sensitivity are determined. It is found that the sensitivity increases linearly with increasing temperature, reaching 890 mV/pH at 75 °C. By using a dual-gate structure and adjusting the control gate voltage, the sensitivity can be reduced from 750 mV/pH at 0 V control gate voltage to 540 mV/pH at 1 V control gate voltage. The above sensitivity changes are produced because the Nernst limit changes with temperature or the electric field generated by different control gate voltages causes changes in the carrier movement. It is proved that a single FDSOI-ISFET can have adjustable sensitivity by adjusting the operating temperature or the control gate voltage of the dual-gate device.

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