Impact of tunnel currents and channel resistance on the characterization of channel inversion layer charge and polysilicon-gate depletion of sub-20-Å gate oxide MOSFETs

1999 ◽  
Vol 46 (8) ◽  
pp. 1650-1655 ◽  
Author(s):  
K. Ahmed ◽  
E. Ibok ◽  
G.C.-F. Yeap ◽  
Qi Xiang ◽  
B. Ogle ◽  
...  
Keyword(s):  
Inversion Layer ◽  
Gate Oxide ◽  
Layer Charge ◽  
Channel Resistance ◽  
Polysilicon Gate

Electrical characterization of fluorine-implanted gate oxide structures

1996 ◽  
Vol 74 (S1) ◽  
pp. 74-78 ◽  
Author(s):  
T. K. Nguyen ◽  
L. M. Landsberger ◽  
V. Logiudice ◽  
C. Jean
Keyword(s):  
Gate Dielectrics ◽  
Electrical Characterization ◽  
Gate Oxide ◽  
Constant Current ◽  
Reliability Indicators ◽  
Polysilicon Gate ◽  
Device Reliability ◽  
Voltage Stress ◽  
Electrical Reliability

In the ongoing quest for thinner and more reliable gate dielectrics for microelectronics, fluorination of gate oxide structures has emerged as a leading technique. In this work, the fluorine is implanted into the polysilicon gate before the poly etch. After the subsequent poly etch and anneal, the samples are not sent through the remainder of the process, but are subjected to electrical reliability stressing by two methods: constant-current Fowler–Nordheim tunnelling stress, and constant-voltage stress (J–t analysis). Two different fluorination cases (doses and implant energies) are studied, along with unimplanted controls. In the fluorinated cases, improvement vs. controls is found in device reliability indicators: mid-gap Dit, Qf, and ΔVth. J–t analysis corroborates the improvement, and the combination of techniques is found to offer a more, comprehensive view of complex variations in fluorinated oxide properties.

Effects of Inversion Layer Quantization and Polysilicon Gate Depletion on Tunneling Current of Ultra-Thin SiO2 Gate Material

1999 ◽  
Vol 567 ◽  
Author(s):  
S. Saha ◽  
G. Srinivasan ◽  
G. A. Rezvani ◽  
M. Farr
Keyword(s):  
Leakage Current ◽  
Supply Voltage ◽  
Inversion Layer ◽  
Gate Oxide ◽  
Oxide Thickness ◽  
Gate Leakage Current ◽  
Gate Leakage ◽  
Polysilicon Gate ◽  
Gate Oxide Thickness ◽  
The Impact

ABSTRACTWe have investigated the impact of inversion layer quantization and polysilicon-gate depletion effects on the direct-tunneling gate-leakage current and reliability of ultra-thin silicon-dioxide gate dielectric. The gate-leakage current was measured for nMOSFET devices with gate oxide thickness down to 3 nm. A simulation-based methodology was used to determine the physical oxide thickness from the measured capacitance data, and the corresponding effective gate oxide thickness at inversion was computed from the simulation data obtained with and without the quantum mechanical and polysilicon depletion effects. The simulation results indicate that the effective gate oxide thickness is significantly higher than the physically grown oxide thickness due to inversion layer quantization and polysilicon depletion effects. The increase in oxide thickness is strongly dependent on the supply voltage and is more than 0.6 nm at 1 V. Our data, also, show that in order to maintain a leakage current ≥ 1 A/cm2 for 1 V operation, the effective gate oxide thickness must be ≥ 2.2 nm.

Physical Failure Analysis Techniques for Front-End-of-Line Defect Analysis

2016 ◽  
Author(s):  
Dirk Doyle ◽  
Lawrence Benedict ◽  
Fritz Christian Awitan
Keyword(s):  
Cross Section ◽  
Focused Ion Beam ◽  
Ion Beam ◽  
Gate Oxide ◽  
Top Down ◽  
New Techniques ◽  
First Case ◽  
Transmission Electron ◽  
Scanning Transmission

Abstract Novel techniques to expose substrate-level defects are presented in this paper. New techniques such as inter-layer dielectric (ILD) thinning, high keV imaging, and XeF2 poly etch overflow are introduced. We describe these techniques as applied to two different defects types at FEOL. In the first case, by using ILD thinning and high keV imaging, coupled with focused ion beam (FIB) cross section and scanning transmission electron microscopy (STEM,) we were able to judge where to sample for TEM from a top down perspective while simultaneously providing the top down images giving both perspectives on the same sample. In the second case we show retention of the poly Si short after removal of CoSi2 formation on poly. Removal of the CoSi2 exposes the poly Si such that we can utilize XeF2 to remove poly without damaging gate oxide to reveal pinhole defects in the gate oxide. Overall, using these techniques have led to 1) increased chances of successfully finding the defects, 2) better characterization of the defects by having a planar view perspective and 3) reduced time in localizing defects compared to performing cross section alone.

Effect of the inversion layer on the electrical characterization of Pt germanide/n-Ge(001) Schottky contacts

2006 ◽  
Vol 89 (24) ◽  
pp. 242117 ◽  
Author(s):  
H. B. Yao ◽  
D. Z. Chi ◽  
R. Li ◽  
S. J. Lee ◽  
D.-L. Kwong
Keyword(s):  
Inversion Layer ◽  
Electrical Characterization ◽  
Schottky Contacts

Stability of Ultra-Thin Gate Oxides with Boron Doped Polysilicon Gate Structures After Rapid Thermal Annealing

1993 ◽  
Vol 303 ◽  
Author(s):  
Bojun Zhang ◽  
Dennis M. Maher ◽  
Mark S. Denker ◽  
Mark A. Ray
Keyword(s):  
Thermal Annealing ◽  
Rapid Thermal Annealing ◽  
Depth Profiling ◽  
Gate Oxide ◽  
Annealing Condition ◽  
Dopant Diffusion ◽  
Boron Diffusion ◽  
Gate Oxides ◽  
Diffusion Behavior ◽  
Polysilicon Gate

ABSTRACTWe report a systematic study of dopant diffusion behavior for thin gate oxides and polysilicon implanted gate structures. Boron behavior is emphasized and its behavior is compared to that of As+ and BF2+. Dopant activation is achieved by rapid thermal annealing. Test structures with 100 Å, 60 Å and 30 Å gate oxides and ion implanted polysilicon gate electrodes were fabricated and characterized after annealing by SIMS, SEM, TEM, and C-V rpeasurements. For arsenic implanted structures, no dopant diffusion through a gate oxide of 30 Å thickness and an annealing condition as high as 1 100*C/1Os was observed. For boron implanted structures, as indicated by SIMS depth profiling, structures annealed at 1000*C/10s exhibit a so-called critical condition for boron diffusion through a 30 Å gate oxide. Boron dopant penetration is clearly observed for 60 Å gate oxides at an annealing condition of 1050 0C/10s. The flatband voltage shift can be as high as 0.56 volts as indicated by C-V measurements for boron penetrated gate oxides. However, 100 Å gate oxides are good diffusion barriers for boron at an annealing condition of 1100°C/10s. For BF2 implanted structures, the diffusion behavior is consistent with behavior reported in the literature.

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