A stochastic wire-length distribution for gigascale integration (GSI). II. Applications to clock frequency, power dissipation, and chip size estimation

1998 ◽  
Vol 45 (3) ◽  
pp. 590-597 ◽  
Author(s):  
J.A. Davis ◽  
V.K. De ◽  
J.D. Meindl
Keyword(s):  
Power Dissipation ◽  
Length Distribution ◽  
Size Estimation ◽  
Wire Length ◽  
Clock Frequency ◽  
Gigascale Integration ◽  
Chip Size ◽  
Frequency Power

Interconnect Limits on Gigascale Integration (GSI)

1997 ◽  
Vol 473 ◽  
Author(s):  
J. A. Davis ◽  
J. D. Meindl
Keyword(s):  
Response Time ◽  
Length Distribution ◽  
Path Model ◽  
System Level ◽  
Wire Length ◽  
Clock Frequency ◽  
Gigascale Integration ◽  
Logic Network ◽  
Binary Switching ◽  
Quantitative Definition

ABSTRACTOpportunities for Gigascale Integration (GSI) are governed by a hierarchy of physical limits. The levels of this hierarchy have been codified as: 1) fundamental, 2) material, 3) device, 4) circuit and 5) system. Many key limits at all levels of the hierarchy can be displayed in the power, P, versus delay, td, plane and the reciprocal length squared, L-2, versus response time, τ, plane. Power, P, is the average power transfer during a binary switching transition and delay, td, is the time required for the transition. Length, L, is the distance traversed by an interconnect that joins two nodes on a chip and response time, τ, characterizes the corresponding interconnect circuit. At the system level of the hierarchy, quantitative definition of both the P versus td and the L-2 versus τ displays requires an estimate of the complete stochastic wiring distribution of a chip.Based on Rent's Rule, a well known empirical relationship between the number of signal input/output terminals on a block of logic and the number of gate circuits with the block, a rigorous derivation of a new complete stochastic wire length distribution for an on-chip random logic network is described. This distribution is compared to actual data for modern microprocessors and to previously described distributions. A methodology for estimating the complete wire length distribution for future GSI products is proposed. The new distribution is then used to enhance the critical path model that determines the maximum clock frequency of a chip; to derive a preliminary power dissipation model for a random logic network; and, to define an optimal architecture of a multilevel interconnect network that minimizes overall chip size. In essence, a new complete stochastic wiring distribution provides a generic basis for maximizing the value obtained from a multilevel interconnect technology.

A Complete Stochastic Wiring Distribution for Gigascale Integration (GSI)

1996 ◽  
Vol 427 ◽  
Author(s):  
Jeffrey A. Davis ◽  
John C. Eble ◽  
Vivek K. De ◽  
James D. Meindl
Keyword(s):  
Empirical Relationship ◽  
Length Distribution ◽  
Gigascale Integration ◽  
Low Dielectric ◽  
Chip Size ◽  
Overall Performance ◽  
Copper Aluminum ◽  
On Chip ◽  
Generic System ◽  
New Distribution

AbstractBased on Rent's Rule, a well established empirical relationship, a rigorous derivation of a complete wire length distribution for on-chip random logic networks is performed. The distribution is then used to describe an optimal architecture for a multilevel wiring network that provides maximum interconnect density and minimum chip size for a ULSI system. In addition, this new distribution has been incorporated into a Generic System Simulator (GENESYS), that projects overall performance of future ULSI systems. Assuming various interconnect materials such as copper, aluminum, silicon dioxide, and low dielectric polymers, GENESYS has been used to examine the effects that each material has on overall performance of ASIC's over the next 15 years.

scholarly journals Power Dissipation of an Inductively Coupled Plasma Torch under E Mode Dominated Regime

Micromachines ◽  
2021 ◽  
Vol 12 (7) ◽  
pp. 834
Author(s):  
Nan Yu ◽  
Renaud Jourdain ◽  
Mustapha Gourma ◽  
Fangda Xu ◽  
Adam Bennett ◽  
...  
Keyword(s):  
Power Dissipation ◽  
Inductively Coupled Plasma ◽  
Plasma Torch ◽  
Electrical Response ◽  
Inductively Coupled ◽  
De Laval Nozzle ◽  
Surface Fabrication ◽  
Icp Torch ◽  
Frequency Power

This paper focuses on the power dissipation of a plasma torch used for an optical surface fabrication process. The process utilizes an inductively coupled plasma (ICP) torch that is equipped with a De-Laval nozzle for the delivery of a highly collimated plasma jet. The plasma torch makes use of a self-igniting coil and an intermediate co-axial tube made of alumina. The torch has a distinctive thermal and electrical response compared to regular ICP torches. In this study, the results of the power dissipation investigation reveal the true efficiency of the torch and discern its electrical response. By systematically measuring the coolant parameters (temperature change and flow rate), the power dissipation is extrapolated. The radio frequency power supply is set to 800 W, E mode, throughout the research presented in this study. The analytical results of power dissipation, derived from the experiments, show that 15.4% and 33.3% are dissipated by the nozzle and coil coolant channels, respectively. The experiments also enable the determination of the thermal time constant of the plasma torch for the entire range of RF power.

AN ULTRA LOW-VOLTAGE/POWER-EFFICIENT ALL-DIGITAL DELAY LOCKED LOOP IN 55 nm CMOS TECHNOLOGY

2012 ◽  
Vol 21 (08) ◽  
pp. 1240025 ◽  
Author(s):  
CHUN-YUAN CHENG ◽  
JINN-SHYAN WANG ◽  
CHENG-TAI YEH
Keyword(s):  
Low Power ◽  
Power Dissipation ◽  
Low Voltage ◽  
Cmos Technology ◽  
Maximum Frequency ◽  
Clock Frequency ◽  
Power Efficient ◽  
Delay Locked Loop ◽  
Measurement Results ◽  
Variation Tolerance

This paper presents an all-digital delay locked loop (ADDLL) that uses asynchronous-deskewing technology and achieves low power/voltage, small jitter, fast locking, and high process, voltage, and temperature (PVT)-variation tolerance. The measurement results show that the maximum frequency is 100 MHz at 0.35 V with 19 μW power dissipation, 62 ps peak-to-peak jitter, and 3 locking cycles. When operated at 0.5 V, the measured maximal operating clock frequency is 450 MHz with 12 ps peak-to-peak jitter, 6 locking cycles and 119 μW power dissipation. The ADDLL is fabricated with 55 nm CMOS technology, and the active area is only 0.019 mm2.

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