Proceedings of the 2003 international workshop on System-level interconnect prediction - SLIP '03
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Validation of wire length distribution models on commercial designs

Proceedings of the 2003 international workshop on System-level interconnect prediction - SLIP '03 ◽

10.1145/639929.639938 ◽

2003 ◽

Author(s):

Martijn Bennebroek

Keyword(s):

Length Distribution ◽

Wire Length ◽

Distribution Models

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Error-correction and crosstalk avoidance in DSM busses

Proceedings of the 2003 international workshop on System-level interconnect prediction - SLIP '03 ◽

10.1145/639929.639933 ◽

2003 ◽

Cited By ~ 8

Author(s):

Ketan N. Patel ◽

Igor L. Markov

Keyword(s):

Error Correction ◽

Crosstalk Avoidance

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Switching activity analysis and pre-layout activity prediction for FPGAs

Proceedings of the 2003 international workshop on System-level interconnect prediction - SLIP '03 ◽

10.1145/639929.639934 ◽

2003 ◽

Cited By ~ 9

Author(s):

Jason H. Anderson ◽

Farid N. Najm

Keyword(s):

Activity Analysis ◽

Switching Activity ◽

Activity Prediction

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Estimation of wirelength reduction for λ-geometry vs. manhattan placement and routing

Proceedings of the 2003 international workshop on System-level interconnect prediction - SLIP '03 ◽

10.1145/639929.639944 ◽

2003 ◽

Cited By ~ 14

Author(s):

Hongyu Chen ◽

Chung-Kuan Cheng ◽

Andrew B. Kahng ◽

Ion Mandoiu ◽

Qinke Wang

Keyword(s):

Placement And Routing

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Fast estimation of the partitioning rent characteristic using a recursive partitioning model

Proceedings of the 2003 international workshop on System-level interconnect prediction - SLIP '03 ◽

10.1145/639929.639940 ◽

2003 ◽

Cited By ~ 1

Author(s):

J. Dambre ◽

D. Stroobandt ◽

J. Van Campenhout

Keyword(s):

Recursive Partitioning ◽

Fast Estimation ◽

Recursive Partitioning Model

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Global interconnect trade-off for technology over memory modules to application level

Proceedings of the 2003 international workshop on System-level interconnect prediction - SLIP '03 ◽

10.1145/639929.639954 ◽

2003 ◽

Cited By ~ 4

Author(s):

A. Papanikolaou ◽

M. Miranda ◽

F. Catthoor ◽

H. Corporaal ◽

H. De Man ◽

...

Keyword(s):

Trade Off ◽

Memory Modules ◽

Global Interconnect

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Sequential delay budgeting with interconnect prediction

Proceedings of the 2003 international workshop on System-level interconnect prediction - SLIP '03 ◽

10.1145/639929.639935 ◽

2003 ◽

Cited By ~ 1

Author(s):

Chao-Yang Yeh ◽

Malgorzata Marek-Sadowska

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Wire length prediction in constraint driven placement

Proceedings of the 2003 international workshop on System-level interconnect prediction - SLIP '03 ◽

10.1145/639929.639950 ◽

2003 ◽

Cited By ~ 3

Author(s):

Qinghua Liu ◽

Bo Hu ◽

Malgorzata Marek-Sadowska

Keyword(s):

Wire Length

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System level interconnect design for network-on-chip using interconnect IPs

Proceedings of the 2003 international workshop on System-level interconnect prediction - SLIP '03 ◽

10.1145/639929.639953 ◽

2003 ◽

Cited By ~ 4

Author(s):

Jian Liu ◽

Meigen Shen ◽

Li-Rong Zheng ◽

Hannu Tenhunen

Keyword(s):

Network On Chip ◽

System Level ◽

Interconnect Design ◽

On Chip

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Placement rent exponent calculation methods, temporal behaviour and FPGA architecture evaluation

Proceedings of the 2003 international workshop on System-level interconnect prediction - SLIP '03 ◽

10.1145/639929.639936 ◽

2003 ◽

Cited By ~ 11

Author(s):

Joachim Pistorius ◽

Mike Hutton

Keyword(s):

Calculation Methods ◽

Temporal Behaviour ◽

Fpga Architecture ◽

Architecture Evaluation

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Proceedings of the 2003 international workshop on System-level interconnect prediction - SLIP '03Latest Publications

TOTAL DOCUMENTS

H-INDEX

Published By ACM Press

Validation of wire length distribution models on commercial designs

Error-correction and crosstalk avoidance in DSM busses

Switching activity analysis and pre-layout activity prediction for FPGAs

Estimation of wirelength reduction for λ-geometry vs. manhattan placement and routing

Fast estimation of the partitioning rent characteristic using a recursive partitioning model

Global interconnect trade-off for technology over memory modules to application level

Sequential delay budgeting with interconnect prediction

Wire length prediction in constraint driven placement

System level interconnect design for network-on-chip using interconnect IPs

Placement rent exponent calculation methods, temporal behaviour and FPGA architecture evaluation

Proceedings of the 2003 international workshop on System-level interconnect prediction - SLIP '03
Latest Publications