Low-noise and high-speed charge detection in high-resolution CCD image sensors

1997 ◽  
Vol 44 (10) ◽  
pp. 1679-1688 ◽  
Author(s):  
J. Hynecek
Keyword(s):  
High Resolution ◽  
High Speed ◽  
Low Noise ◽  
Image Sensors ◽  
Charge Detection ◽  
Ccd Image

High-speed dual-output-channel stage-selectable TDI CCD image sensor for high-resolution applications

1995 ◽  
Author(s):  
M. S. Agwani ◽  
David A. Dobson ◽  
William D. Washkurak ◽  
Savvas G. Chamberlain
Keyword(s):  
High Resolution ◽  
High Speed ◽  
Image Sensor ◽  
Output Channel ◽  
Ccd Image Sensor ◽  
Ccd Image

High Speed Document Scanner Using Charge Coupled Device (CCD) Image Sensors

1983 ◽  
Author(s):  
Masahiro Mori ◽  
Isao Kondo ◽  
Masakatsu Horie
Keyword(s):  
High Speed ◽  
Image Sensors ◽  
Charge Coupled Device ◽  
Ccd Image

High-resolution CCD image sensors with reduced smear

1985 ◽  
Vol 32 (8) ◽  
pp. 1451-1456 ◽  
Author(s):  
T. Kumesawa ◽  
M. Yamamura ◽  
H. Terakawa ◽  
H. Murata ◽  
H. Matsumoto ◽  
...  
Keyword(s):  
High Resolution ◽  
Image Sensors ◽  
Ccd Image

A LOW POWER HIGH RESOLUTION ROIC DESIGN WITH 14-BIT COLUMN-LEVEL ADC FOR 384 × 288 IRFPA

2013 ◽  
Vol 22 (09) ◽  
pp. 1340015 ◽  
Author(s):  
YAJING ZHANG ◽  
WENGAO LU ◽  
GUANNAN WANG ◽  
ZHONGJIAN CHEN ◽  
YACONG ZHANG
Keyword(s):  
High Resolution ◽  
Low Power ◽  
Integrated Circuit ◽  
High Speed ◽  
High Performance ◽  
Low Noise ◽  
Cmos Process ◽  
Readout Integrated Circuit ◽  
Analog To Digital Conversion ◽  
Amplifier Design

A readout integrated circuit (ROIC) of infrared focal plane array (IRFPA) with low power and low noise is presented in this paper. It consists of a 384 × 288 pixel array and column-level A/D conversion circuits. The proposed system has high resolution because of the odd–even Analog to Digital Conversion (ADC) structure, containing correlated switches design, multi-Vth amplifier design and high speed high resolution comparator design including latch-stage. Designed and simulated in 0.35-μm CMOS process, this high performance ROIC achieves 81.24 dB SNR at 8.64 KS/s consuming 98 mW under 5 V voltage supply, resulting in an ENOB of 13.2-bit.

The Multi-Channel Data Acquisition System Based on FPGA and ADS1252

2014 ◽  
Vol 543-547 ◽  
pp. 2440-2443
Author(s):  
Bing Qi Liu ◽  
Ming Zhe Liu ◽  
Xin Jiang ◽  
Xiao Bo Mao ◽  
Tong Shen
Keyword(s):  
High Resolution ◽  
Data Acquisition ◽  
High Speed ◽  
Data Acquisition System ◽  
Low Noise ◽  
Acquisition System ◽  
Validity And Reliability ◽  
Parallel Acquisition ◽  
Noise Interference ◽  
Clock Domains

In this article, a design of multi-channel data acquisition system is presented. With FPGA as the core controller, the system can implement logic control over the high-speed ADC and acquire high-speed and high-resolution sample data. Using asynchronous FIFO as a cache, it can transfer data between two different clock domains: ADC data acquisition module and RS485 data module, which helps to improve the work efficiency and data throughput of the system. In the Quartus II development platform, Verilog hardware description language is adopted and finite state machine so that parallel acquisition operation to multi-channel ADC controlled by FPGA can be achieved and the system can become equipped with high-resolution, strong real-timeliness, low noise interference and other advantages. When it comes to the final step, simulation of AD sampling, asynchronous FIFO and RS485 transmission are conducted under the Modelsim environment and on-line testing by Signaltap to the system is synchronously implemented. The validity and reliability of the system are verified.

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