Ga/sub 0.51/In/sub 0.49/P/GaAs HEMT's exhibiting good electrical performance at cryogenic temperatures

1990 ◽  
Vol 37 (10) ◽  
pp. 2141-2147 ◽  
Author(s):  
Y.-J. Chan ◽  
D. Pavlidis ◽  
M. Razeghi ◽  
F. Omnes
2015 ◽  
Vol 785 ◽  
pp. 325-329
Author(s):  
N.A.M. Jamail ◽  
M.A.M. Piah ◽  
Nor Asiah Muhamad ◽  
Hanafiah Kamarden ◽  
Qamarul Ezani Kamarudin

Polymeric nanocomposites are widely used for high voltage outdoor insulating application due to their good electrical performance. Recently, SiO2, TiO2 and MMT nanofillers are being used as filler because there are listed as main nanofiller commonly used in electrical engineering. Natural rubber (NR) was used because the nature of the interphase is found to affect viscoelasticity and it develops several interphases with the Linear Low-Density Polyethylene (LLDPE) matrix. One of the problems associated with outdoor polymeric insulators is tracking of the surface which can directly influence the reliability of the insulator. This paper presents the outcome of an experimental study to determine the conductivity level of the LLDPE-NR compound, filled with different amount of SiO2, TiO2 and MMT nanofiller using Polarization and Depolarization Current (PDC) measurement technique. LLDPE and NR with the ratio composition of 80:20 were selected as a base polymer. Results show that different compositions as well as the surface physical conditions affect the PDC measurement results.


2020 ◽  
Vol 1486 ◽  
pp. 062007
Author(s):  
Chang Zhou ◽  
Jing Xia ◽  
Wanwan Jin ◽  
Li Wang ◽  
Gang Liu ◽  
...  

1998 ◽  
Vol 514 ◽  
Author(s):  
M. Brillouët

ABSTRACTThe performance and cost of the logic ICs is more and more dominated by the interconnections. Reducing the capacitances in the advanced processes, especially with low k dielectrics, is a priority, while a differentiated approach can be applied for lowering the connection resistances, e.g. in adapting the interconnect material to specific levels. Integrating new materials leads to difficult trade-offs in order to achieve a good electrical performance of the circuit. Finally the increased number of levels of interconnection addresses other fields like integration density, defectivity reduction or cost.


1999 ◽  
Author(s):  
Matthias Heschel ◽  
Kurt Rasmussen ◽  
Jochen F. Kuhmann ◽  
Siebe Bouwstra

Abstract This paper describes a novel technology for multiple wafer frontside to backside interconnects, which has been applied to a multifunctional interconnect layer for an integrated microphone for hearing aid applications. Besides the interconnect layer with relatively large through-holes the stack consists of the microphone itself and an integrated circuit chip for signal conditioning. The patterning of the metallization on the interconnect wafer has been done using electrodepositable photoresist as mold for electroplating of a variety of metals. For the interconnect metallization we use copper. The bonding pads on the microphone side of the interconnect layer have been provided with under bump metallizations (UBM) and solder bumps. The IC side features a top surface metallization (TSM) suitable for conductive adhesive bonding. The realized feedthrough wires show good electrical performance in terms of low series resistance (100 mΩ) and small parasitic capacitance (< 1 pF).


2000 ◽  
Vol 660 ◽  
Author(s):  
John A. Rogers ◽  
Kirk Baldwin ◽  
Zhenan Bao ◽  
Ananth Dodabalapur ◽  
V.R. Raju ◽  
...  

ABSTRACTThis paper illustrates the use of a high resolution form of rubber stamping, known as microcontact printing (μCP), for patterning plastic active matrix drive circuitry designed for electronic paper. The high resolution (∼1 [.mu]m) of the printed elements, the large area coverage (∼1 sq. ft.) and the good electrical performance of these systems suggest that the methods, materials and processing sequences may be attractive for realistic applications of plastic electronics.


Author(s):  
K. A. Fisher ◽  
M. G. L. Gustafsson ◽  
M. B. Shattuck ◽  
J. Clarke

The atomic force microscope (AFM) is capable of imaging electrically conductive and non-conductive surfaces at atomic resolution. When used to image biological samples, however, lateral resolution is often limited to nanometer levels, due primarily to AFM tip/sample interactions. Several approaches to immobilize and stabilize soft or flexible molecules for AFM have been examined, notably, tethering coating, and freezing. Although each approach has its advantages and disadvantages, rapid freezing techniques have the special advantage of avoiding chemical perturbation, and minimizing physical disruption of the sample. Scanning with an AFM at cryogenic temperatures has the potential to image frozen biomolecules at high resolution. We have constructed a force microscope capable of operating immersed in liquid n-pentane and have tested its performance at room temperature with carbon and metal-coated samples, and at 143° K with uncoated ferritin and purple membrane (PM).


Author(s):  
L. M. Gignac ◽  
K. P. Rodbell

As advanced semiconductor device features shrink, grain boundaries and interfaces become increasingly more important to the properties of thin metal films. With film thicknesses decreasing to the range of 10 nm and the corresponding features also decreasing to sub-micrometer sizes, interface and grain boundary properties become dominant. In this regime the details of the surfaces and grain boundaries dictate the interactions between film layers and the subsequent electrical properties. Therefore it is necessary to accurately characterize these materials on the proper length scale in order to first understand and then to improve the device effectiveness. In this talk we will examine the importance of microstructural characterization of thin metal films used in semiconductor devices and show how microstructure can influence the electrical performance. Specifically, we will review Co and Ti silicides for silicon contact and gate conductor applications, Ti/TiN liner films used for adhesion and diffusion barriers in chemical vapor deposited (CVD) tungsten vertical wiring (vias) and Ti/AlCu/Ti-TiN films used as planar interconnect metal lines.


2020 ◽  
Vol 91 (3) ◽  
pp. 30201
Author(s):  
Hang Yu ◽  
Jianlin Zhou ◽  
Yuanyuan Hao ◽  
Yao Ni

Organic thin film transistors (OTFTs) based on dioctylbenzothienobenzothiophene (C8BTBT) and copper (Cu) electrodes were fabricated. For improving the electrical performance of the original devices, the different modifications were attempted to insert in three different positions including semiconductor/electrode interface, semiconductor bulk inside and semiconductor/insulator interface. In detail, 4,4′,4′′-tris[3-methylpheny(phenyl)amino] triphenylamine (m-MTDATA) was applied between C8BTBTand Cu electrodes as hole injection layer (HIL). Moreover, the fluorinated copper phthalo-cyanine (F16CuPc) was inserted in C8BTBT/SiO2 interface to form F16CuPc/C8BTBT heterojunction or C8BTBT bulk to form C8BTBT/F16CuPc/C8BTBT sandwich configuration. Our experiment shows that, the sandwich structured OTFTs have a significant performance enhancement when appropriate thickness modification is chosen, comparing with original C8BTBT devices. Then, even the low work function metal Cu was applied, a normal p-type operate-mode C8BTBT-OTFT with mobility as high as 2.56 cm2/Vs has been fabricated.


2002 ◽  
Vol 716 ◽  
Author(s):  
Yi-Mu Lee ◽  
Yider Wu ◽  
Joon Goo Hong ◽  
Gerald Lucovsky

AbstractConstant current stress (CCS) has been used to investigate the Stress-Induced Leakage Current (SILC) to clarify the influence of boron penetration and nitrogen incorporation on the breakdown of p-channel devices with sub-2.0 nm Oxide/Nitride (O/N) and oxynitride dielectrics prepared by remote plasma enhanced CVD (RPECVD). Degradation of MOSFET characteristics correlated with soft breakdown (SBD) and hard breakdown (HBD), and attributed to the increased gate leakage current are studied. Gate voltages were gradually decreased during SBD, and a continuous increase in SILC at low gate voltages between each stress interval, is shown to be due to the generation of positive traps which are enhanced by boron penetration. Compared to thermal oxides, stacked O/N and oxynitride dielectrics with interface nitridation show reduced SILC due to the suppression of boron penetration and associated positive trap generation. Devices stressed under substrate injection show harder breakdown and more severe degradation, implying a greater amount of the stress-induced defects at SiO2/substrate interface. Stacked O/N and oxynitride devices also show less degradation in electrical performance compared to thermal oxide devices due to an improved Si/SiO2 interface, and reduced gate-to-drain overlap region.


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