A high performance super self-aligned 3 V/5 V BiCMOS technology with extremely low parasitics for low-power mixed-signal applications

1995 ◽  
Vol 42 (3) ◽  
pp. 513-522 ◽  
Author(s):  
J.M. Sung ◽  
T.-Y. Chiu ◽  
K. Lau ◽  
T.M. Liu ◽  
V.D. Archer ◽  
...  
Keyword(s):  
Low Power ◽  
High Performance ◽  
Mixed Signal ◽  
Bicmos Technology

A mixed-signal approach to high-performance low-power linear filters

2001 ◽  
Vol 36 (5) ◽  
pp. 816-822 ◽  
Author(s):  
W. Figueroa ◽  
D. Hsu ◽  
C. Diorio
Keyword(s):  
Low Power ◽  
High Performance ◽  
Linear Filters ◽  
Mixed Signal ◽  
Signal Approach

RECENT ADVANCES IN BiCMOS TECHNOLOGY

1990 ◽  
Vol 01 (02) ◽  
pp. 153-167
Author(s):  
TZU-YIN CHIU ◽  
PING K. KO
Keyword(s):  
Low Power ◽  
High Speed ◽  
High Performance ◽  
Technology Evolution ◽  
Recent Advances ◽  
Bicmos Technology ◽  
Device Structures ◽  
High Performance Systems ◽  
Technology Trend

The merits of high speed bipolar and low power VLSI CMOS are combined in BiCMOS technology. Designers are exploiting additional dimensions of flexibility and are implementing aggressive high performance systems not achievable before. Various approaches to BiCMOS integration, spanning from a single mask addition to sophisticated fully self-aligned device structures, are reviewed in this article. The philosophies behind the technology evolution in the last five years are discussed. We have also ventured to extrapolate future BiCMOS technology trend and applications.

Efficient Instruction and Data Caching for High Performance Embedded Processors

1970 ◽  
pp. 9
Author(s):  
A. Ferrerón Labari ◽  
D. Suárez Gracia ◽  
V. Viñals Yúfera
Keyword(s):  
Embedded Systems ◽  
Power Consumption ◽  
Low Power ◽  
Interconnection Networks ◽  
High Performance ◽  
Critical Issue ◽  
Content Management ◽  
Structure Design ◽  
Portable Devices ◽  
On Chip

In the last years, embedded systems have evolved so that they offer capabilities we could only find before in high performance systems. Portable devices already have multiprocessors on-chip (such as PowerPC 476FP or ARM Cortex A9 MP), usually multi-threaded, and a powerful multi-level cache memory hierarchy on-chip. As most of these systems are battery-powered, the power consumption becomes a critical issue. Achieving high performance and low power consumption is a high complexity challenge where some proposals have been already made. Suarez et al. proposed a new cache hierarchy on-chip, the LP-NUCA (Low Power NUCA), which is able to reduce the access latency taking advantage of NUCA (Non-Uniform Cache Architectures) properties. The key points are decoupling the functionality, and utilizing three specialized networks on-chip. This structure has been proved to be efficient for data hierarchies, achieving a good performance and reducing the energy consumption. On the other hand, instruction caches have different requirements and characteristics than data caches, contradicting the low-power embedded systems requirements, especially in SMT (simultaneous multi-threading) environments. We want to study the benefits of utilizing small tiled caches for the instruction hierarchy, so we propose a new design, ID-LP-NUCAs. Thus, we need to re-evaluate completely our previous design in terms of structure design, interconnection networks (including topologies, flow control and routing), content management (with special interest in hardware/software content allocation policies), and structure sharing. In CMP environments (chip multiprocessors) with parallel workloads, coherence plays an important role, and must be taken into consideration.

High-Performance and Low-Power Full Color Reflective LCD for New Applications

2019 ◽  
pp. 1411
Author(s):  
Hiroyuki Hakoi ◽  
Ming Ni ◽  
Junichi Hashimoto ◽  
Takashi Sato ◽  
Shinji Shimada ◽  
...  
Keyword(s):  
Low Power ◽  
High Performance ◽  
Full Color ◽  
New Applications
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