Electrochemical C-V profiling of heterojunction device structures

1989 ◽  
Vol 36 (2) ◽  
pp. 309-313 ◽  
Author(s):  
A.C. Seabaugh ◽  
W.R. Frensley ◽  
R.J. Matyi ◽  
G.E. Cabaniss
Keyword(s):  
Device Structures ◽  
Heterojunction Device

Electrical characteristics of lateral organic bulk heterojunction device structures

2012 ◽  
Vol 13 (7) ◽  
pp. 1185-1191 ◽  
Author(s):  
Christopher Lombardo ◽  
Zi-En Ooi ◽  
Eric Danielson ◽  
Ananth Dodabalapur
Keyword(s):  
Bulk Heterojunction ◽  
Electrical Characteristics ◽  
Device Structures ◽  
Heterojunction Device

Contact-Free Determination of Scattering Times in Heterojunction Device Structures

1992 ◽  
Vol 281 ◽  
Author(s):  
P. Omling ◽  
H. Linke ◽  
P. Ramvall ◽  
B. K. Meyer
Keyword(s):  
High Speed ◽  
Measurement Techniques ◽  
Far Infrared ◽  
Device Structures ◽  
Far Infrared Lasers ◽  
Heterojunction Device ◽  
Shubnikov De Haas Oscillations ◽  
Optically Detected ◽  
Contact Free

ABSTRACTIn this paper we present contact-free measurement techniques which are important for the evaluation of heterojunctions of interest for optical as well as high-speed devices. The techniques are the microwave-detection of Shubnikov-de Haas oscillations, photoluminescence-detected magneto-oscillations, and optically detected cyclotron resonance using microwaves (ODCR) as well as far-infrared lasers (FIR-ODCR). The techniques are illustrated by several examples, and the possibilities to determine 2D carrier concentrations, effective masses, and scattering times in the heterojunction structures are discussed.

Properties of DX Centers in AlxGa1−xAs and Effects on Heterojunction Devices

1990 ◽  
Vol 184 ◽  
Author(s):  
P. M. Mooney
Keyword(s):  
Experimental Results ◽  
Dx Centers ◽  
Local Atomic Environment ◽  
Heterojunction Devices ◽  
Microscopic Models ◽  
Device Structures ◽  
Heterojunction Device ◽  
Dx Center

ABSTRACTIn this paper the effects of DX levels on the properties of AlxGa1−xAs and certain heterojunction device structures are summarized. Studies of alloy effects, variations of the local atomic environment near the donor, are reviewed and microscopic models of the DX center are discussed in terms of these and other recent experimental results.

A technique to prepare cross-sectional TEM specimens of semiconducting devices

1986 ◽  
Vol 44 ◽  
pp. 742-743
Author(s):  
A. K. Rai ◽  
P. P. Pronko
Keyword(s):  
Thin Films ◽  
Surface Region ◽  
Sample Surface ◽  
Specific Region ◽  
Cross Sectional ◽  
Thin Sections ◽  
The Past ◽  
Device Structures ◽  
Ion Implanted

Several techniques have been reported in the past to prepare cross(x)-sectional TEM specimen. These methods are applicable when the sample surface is uniform. Examples of samples having uniform surfaces are ion implanted samples, thin films deposited on substrates and epilayers grown on substrates. Once device structures are fabricated on the surfaces of appropriate materials these surfaces will no longer remain uniform. For samples with uniform surfaces it does not matter which part of the surface region remains in the thin sections of the x-sectional TEM specimen since it is similar everywhere. However, in order to study a specific region of a device employing x-sectional TEM, one has to make sure that the desired region is thinned. In the present work a simple way to obtain thin sections of desired device region is described.

Behavior of contact-silicided TFSOI gate structures

1994 ◽  
Vol 52 ◽  
pp. 860-861
Author(s):  
N. David Theodore ◽  
Juergen Foerstner ◽  
Peter Fejes
Keyword(s):  
Semiconductor Device ◽  
Series Resistance ◽  
Field Effect Transistors ◽  
Silicon Layer ◽  
Device Fabrication ◽  
Silicon On Insulator ◽  
Continuous Layer ◽  
Buried Oxide ◽  
Device Structures ◽  
Thin Silicon

As semiconductor device dimensions shrink and packing-densities rise, issues of parasitic capacitance and circuit speed become increasingly important. The use of thin-film silicon-on-insulator (TFSOI) substrates for device fabrication is being explored in order to increase switching speeds. One version of TFSOI being explored for device fabrication is SIMOX (Silicon-separation by Implanted OXygen).A buried oxide layer is created by highdose oxygen implantation into silicon wafers followed by annealing to cause coalescence of oxide regions into a continuous layer. A thin silicon layer remains above the buried oxide (~220 nm Si after additional thinning). Device structures can now be fabricated upon this thin silicon layer.Current fabrication of metal-oxidesemiconductor field-effect transistors (MOSFETs) requires formation of a polysilicon/oxide gate between source and drain regions. Contact to the source/drain and gate regions is typically made by use of TiSi2 layers followedby Al(Cu) metal lines. TiSi2 has a relatively low contact resistance and reduces the series resistance of both source/drain as well as gate regions

Defect morphology in thick relaxed layers of InGaAs on GaAs

1990 ◽  
Vol 48 (4) ◽  
pp. 668-669
Author(s):  
R H Dixon ◽  
P Kidd ◽  
P J Goodhew
Keyword(s):  
Electron Microscopy ◽  
Surface Morphology ◽  
Growth Conditions ◽  
X Ray Diffraction ◽  
Double Crystal ◽  
Strained Layers ◽  
Good Surface ◽  
Transmission Electron ◽  
Device Structures ◽  
Surface Morphologies

Thick relaxed InGaAs layers grown epitaxially on GaAs are potentially useful substrates for growing high indium percentage strained layers. It is important that these relaxed layers are defect free and have a good surface morphology for the subsequent growth of device structures.3μm relaxed layers of InxGa1-xAs were grown on semi - insulating GaAs substrates by Molecular Beam Epitaxy (MBE), where the indium composition ranged from x=0.1 to 1.0. The interface, bulk and surface of the layers have been examined in planar view and cross-section by Transmission Electron Microscopy (TEM). The surface morphologies have been characterised by Scanning Electron Microscopy (SEM), and the bulk lattice perfection of the layers assessed using Double Crystal X-ray Diffraction (DCXRD).The surface morphology has been found to correlate with the growth conditions, with the type of defects grown-in to the layer (e.g. stacking faults, microtwins), and with the nature and density of dislocations in the interface.

ELECTRON BEAM SOURCE MOLECULAR BEAM EPITAXY OF AlxGa1-xAs GRADED BAND GAP DEVICE STRUCTURES

1988 ◽  
Vol 49 (C4) ◽  
pp. C4-607-C4-614
Author(s):  
R. J. MALIK ◽  
A. F.J. LEVI ◽  
B. F. LEVINE ◽  
R. C. MILLER ◽  
D. V. LANG ◽  
...  
Keyword(s):  
Electron Beam ◽  
Molecular Beam Epitaxy ◽  
Band Gap ◽  
Molecular Beam ◽  
Beam Source ◽  
Device Structures ◽  
Graded Band Gap

Automated Diagonal Slice and View Solution for 3D Device Structure Analysis

2018 ◽  
Author(s):  
Sang Hoon Lee ◽  
Jeff Blackwood ◽  
Stacey Stone ◽  
Michael Schmidt ◽  
Mark Williamson ◽  
...  
Keyword(s):  
Cross Section ◽  
Focused Ion Beam ◽  
Ion Beam ◽  
Image Data ◽  
Planar Surface ◽  
Device Structure ◽  
Cross Sectional ◽  
Device Structures ◽  
The Cross ◽  
Planar Analysis

Abstract The cross-sectional and planar analysis of current generation 3D device structures can be analyzed using a single Focused Ion Beam (FIB) mill. This is achieved using a diagonal milling technique that exposes a multilayer planar surface as well as the cross-section. this provides image data allowing for an efficient method to monitor the fabrication process and find device design errors. This process saves tremendous sample-to-data time, decreasing it from days to hours while still providing precise defect and structure data.

TEM Sample Preparation by Single-Sided Low-Energy Ion Beam Etching

2011 ◽  
Author(s):  
Liew Kaeng Nan ◽  
Lee Meng Lung
Keyword(s):  
Sample Preparation ◽  
Semiconductor Device ◽  
Ion Beam ◽  
Critical Dimension ◽  
Low Energy ◽  
Ex Situ ◽  
Good Image Quality ◽  
Ion Beam Etching ◽  
Device Structures ◽  
Common Technique

Abstract Conventional FIB ex-situ lift-out is the most common technique for TEM sample preparation. However, the scaling of semiconductor device structures poses great challenge to the method since the critical dimension of device becomes smaller than normal TEM sample thickness. In this paper, a technique combining 30 keV FIB milling and 3 keV ion beam etching is introduced to prepare the TEM specimen. It can be used by existing FIBs that are not equipped with low-energy ion beam. By this method, the overlapping pattern can be eliminated while maintaining good image quality.

Effects of Backside Circuit Edit on Transistor Characteristics

2007 ◽  
Author(s):  
R.K. Jain ◽  
T. Malik ◽  
T.R. Lundquist ◽  
Q.S. Wang ◽  
R. Schlangen ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Flip Chip ◽  
Intrinsic Parameters ◽  
Chip Type ◽  
Device Structures ◽  
Before And After ◽  
Silicon Device ◽  
Metal Layers

Abstract Backside circuit edit techniques on integrated circuits (ICs) are becoming common due to increase number of metal layers and flip chip type packaging. However, a thorough study of the effects of these modifications has not been published. This in spite of the fact that the IC engineers have sometimes wondered about the effects of backside circuit edit on IC behavior. The IC industry was well aware that modifications can lead to an alteration of the intrinsic behavior of a circuit after a FIB edit [1]. However, because alterations can be controlled [2], they have not stopped the IC industry from using the FIB to successfully reconfigure ICs to produce working “silicon” to prove design and mask changes. Reliability of silicon device structures, transistors and diodes, are investigated by monitoring intrinsic parameters before and after various steps of modification.

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