Back-gate bias effect on the subthreshold behavior and the switching performance in an ultrathin SOI CMOS inverter operating at 77 and 300 K

1992 ◽  
Vol 39 (12) ◽  
pp. 2781-2790 ◽  
Author(s):  
J.B. Kuo ◽  
W.C. Lee ◽  
J.-H. Sim
Keyword(s):  
Gate Bias ◽  
Cmos Inverter ◽  
Bias Effect ◽  
Back Gate ◽  
Switching Performance ◽  
Ultrathin Soi ◽  
Soi Cmos

Suppression of Timing Variations due to Random Dopant Fluctuation by Back-Gate Bias in a Nanometer CMOS Inverter

2020 ◽  
Vol 13 ◽  
Author(s):  
Kai Zhang ◽  
Weifeng Lü ◽  
Peng Si ◽  
Zhifeng Zhao ◽  
Tianyu Yu
Keyword(s):  
Monte Carlo ◽  
Integrated Circuits ◽  
Metal Oxide ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Gate Bias ◽  
Cmos Inverter ◽  
Back Gate ◽  
Random Dopant Fluctuation ◽  
Random Dopant

Background: In state-of-the-art nanometer metal-oxide-semiconductor-field-effect- transistors (MOSFETs), optimization of timing characteristic is one of the major concerns in the design of modern digital integrated circuits. Objective: This study proposes an effective back-gate-biasing technique to comprehensively investigate the timing and its variation due to random dopant fluctuation (RDF) employing Monte Carlo methodology. Methods: To analyze RDF-induced timing variation in a 22-nm complementary metal-oxide semiconductor (CMOS) inverter, an ensemble of 1000 different samples of channel-doping for negative metal-oxide semiconductor (NMOS) and positive metal-oxide semiconductor (PMOS) was reproduced and the input/output curves were measured. Since back-gate bias is technology dependent, we present in parallel results with and without VBG. Results: It is found that the suppression of RDF-induced timing variations can be achieved by appropriately adopting back-gate voltage (VBG) through measurements and detailed Monte Carlo simulations. Consequently, the timing parameters and their variations are reduced and, moreover, that they are also insensitive to channel doping with back-gate bias. Conclusion: Circuit designers can appropriately use back-gate bias to minimize timing variations and improve the performance of CMOS integrated circuits.

scholarly journals Back-gate bias effect on partially depleted SOI/MOS back-gate performances under radiation condition

2012 ◽  
Vol 61 (20) ◽  
pp. 206102
Author(s):  
Zhou Xin-Jie ◽  
Li Lei-Lei ◽  
Zhou Yi ◽  
Luo Jing ◽  
Yu Zong-Guang
Keyword(s):  
Radiation Condition ◽  
Gate Bias ◽  
Bias Effect ◽  
Back Gate

Back-gate bias effect on nanosheet hybrid P/N channel of junctionless thin-film transistor with increased Ion versus decreased Ioff

2015 ◽  
Vol 107 (18) ◽  
pp. 182105 ◽  
Author(s):  
Ya-Chi Cheng ◽  
Hung-Bin Chen ◽  
Chun-Yen Chang ◽  
Yi-Kang Wu ◽  
Yi-Jia Shih ◽  
...  
Keyword(s):  
Thin Film ◽  
Thin Film Transistor ◽  
Gate Bias ◽  
Bias Effect ◽  
Back Gate
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