Back-gate bias effect on nanosheet hybrid P/N channel of junctionless thin-film transistor with increased Ion versus decreased Ioff

2015 ◽  
Vol 107 (18) ◽  
pp. 182105 ◽  
Author(s):  
Ya-Chi Cheng ◽  
Hung-Bin Chen ◽  
Chun-Yen Chang ◽  
Yi-Kang Wu ◽  
Yi-Jia Shih ◽  
...  
Keyword(s):  
Thin Film ◽  
Thin Film Transistor ◽  
Gate Bias ◽  
Bias Effect ◽  
Back Gate

Dependence of persistent photocurrent on gate bias in inkjet printed organic thin-film transistor

2010 ◽  
Vol 96 (12) ◽  
pp. 123301 ◽  
Author(s):  
Chang Hyun Kim ◽  
Min Hee Choi ◽  
Sun Hee Lee ◽  
Jin Jang ◽  
Stephan Kirchmeyer
Keyword(s):  
Thin Film ◽  
Thin Film Transistor ◽  
Gate Bias ◽  
Organic Thin Film ◽  
Organic Thin Film Transistor

Investigating the degradation behavior caused by charge trapping effect under DC and AC gate-bias stress for InGaZnO thin film transistor

2011 ◽  
Vol 99 (2) ◽  
pp. 022104 ◽  
Author(s):  
Te-Chih Chen ◽  
Ting-Chang Chang ◽  
Tien-Yu Hsieh ◽  
Wei-Siang Lu ◽  
Fu-Yen Jian ◽  
...  
Keyword(s):  
Thin Film ◽  
Thin Film Transistor ◽  
Charge Trapping ◽  
Gate Bias ◽  
Degradation Behavior ◽  
Bias Stress ◽  
Trapping Effect ◽  
Gate Bias Stress

Impacts of O₂ Plasma on Negative Gate Bias Stress Instability of Tunnel Thin-Film Transistor

2020 ◽  
pp. 1-6
Author(s):  
William Cheng-Yu Ma ◽  
Po-Jen Chen ◽  
Yan-Shiuan Chang ◽  
Jhe-Wei Jhu ◽  
Ting-Hsuan Chang
Keyword(s):  
Thin Film ◽  
Thin Film Transistor ◽  
Gate Bias ◽  
Bias Stress ◽  
Gate Bias Stress

scholarly journals Voltage-Polarity Dependent Programming Behaviors of Amorphous In–Ga–Zn–O Thin-Film Transistor Memory with an Atomic-Layer-Deposited ZnO Charge Trapping Layer

2019 ◽  
Vol 14 (1) ◽  
Author(s):  
Dan-Dan Liu ◽  
Wen-Jun Liu ◽  
Jun-Xiang Pei ◽  
Lin-Yan Xie ◽  
Jingyong Huo ◽  
...  
Keyword(s):  
Thin Film ◽  
Oxygen Vacancy ◽  
Gate Voltage ◽  
Oxygen Vacancies ◽  
Thin Film Transistor ◽  
Charge Trapping ◽  
Atomic Layer ◽  
Gate Bias ◽  
Voltage Polarity ◽  
Bias Pulse

AbstractAmorphous In–Ga–Zn-O (a-IGZO) thin-film transistor (TFT) memories are attracting many interests for future system-on-panel applications; however, they usually exhibit a poor erasing efficiency. In this article, we investigate voltage-polarity-dependent programming behaviors of an a-IGZO TFT memory with an atomic-layer-deposited ZnO charge trapping layer (CTL). The pristine devices demonstrate electrically programmable characteristics not only under positive gate biases but also under negative gate biases. In particular, the latter can generate a much higher programming efficiency than the former. Upon applying a gate bias pulse of +13 V/1 μs, the device shows a threshold voltage shift (ΔVth) of 2 V; and the ΔVth is as large as −6.5 V for a gate bias pulse of −13 V/1 μs. In the case of 12 V/1 ms programming (P) and −12 V/10 μs erasing (E), a memory window as large as 7.2 V can be achieved at 103 of P/E cycles. By comparing the ZnO CTLs annealed in O2 or N2 with the as-deposited one, it is concluded that the oxygen vacancy (VO)-related defects dominate the bipolar programming characteristics of the TFT memory devices. For programming at positive gate voltage, electrons are injected from the IGZO channel into the ZnO layer and preferentially trapped at deep levels of singly ionized oxygen vacancy (VO+) and doubly ionized oxygen vacancy (VO2+). Regarding programming at negative gate voltage, electrons are de-trapped easily from neutral oxygen vacancies because of shallow donors and tunnel back to the channel. This thus leads to highly efficient erasing by the formation of additional ionized oxygen vacancies with positive charges.

scholarly journals Back-gate bias effect on partially depleted SOI/MOS back-gate performances under radiation condition

2012 ◽  
Vol 61 (20) ◽  
pp. 206102
Author(s):  
Zhou Xin-Jie ◽  
Li Lei-Lei ◽  
Zhou Yi ◽  
Luo Jing ◽  
Yu Zong-Guang
Keyword(s):  
Radiation Condition ◽  
Gate Bias ◽  
Bias Effect ◽  
Back Gate
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