On mapping algorithms to linear and fault-tolerant systolic arrays

V.K.P. Kumar; Y.-C. Tsai

doi:10.1109/12.21135

On mapping algorithms to linear and fault-tolerant systolic arrays

IEEE Transactions on Computers ◽

10.1109/12.21135 ◽

1989 ◽

Vol 38 (3) ◽

pp. 470-478 ◽

Cited By ~ 16

Author(s):

V.K.P. Kumar ◽

Y.-C. Tsai

Keyword(s):

Fault Tolerant ◽

Systolic Arrays ◽

Mapping Algorithms

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On the design of fault-tolerant two-dimensional systolic arrays for yield enhancement

IEEE Transactions on Computers ◽

10.1109/12.21144 ◽

1989 ◽

Vol 38 (4) ◽

pp. 515-525 ◽

Cited By ~ 42

Author(s):

J.H. Kim ◽

S.M. Reddy

Keyword(s):

Fault Tolerant ◽

Yield Enhancement ◽

Systolic Arrays ◽

Two Dimensional

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Restructuring for fault-tolerant systolic arrays

IEEE Transactions on Computers ◽

10.1109/12.16511 ◽

1989 ◽

Vol 38 (2) ◽

pp. 307-311 ◽

Cited By ~ 9

Author(s):

H.F. Li ◽

R. Jayakumar ◽

C. Lam

Keyword(s):

Fault Tolerant ◽

Systolic Arrays

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Link sharing scheme for fault tolerant systolic arrays based on mixed spatial-temporal triple modular redundancy

Proceedings of APCCAS'96 - Asia Pacific Conference on Circuits and Systems ◽

10.1109/apcas.1996.569316 ◽

2002 ◽

Author(s):

M. Kaneko ◽

H. Miyauchi ◽

Choon-Sik Park

Keyword(s):

Fault Tolerant ◽

Systolic Arrays ◽

Triple Modular Redundancy ◽

Sharing Scheme ◽

Modular Redundancy

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Partitioning and Mapping Algorithms into Fixed Size Systolic Arrays

IEEE Transactions on Computers ◽

10.1109/tc.1986.1676652 ◽

1986 ◽

Vol C-35 (1) ◽

pp. 1-12 ◽

Cited By ~ 366

Author(s):

Moldovan ◽

Fortes

Keyword(s):

Systolic Arrays ◽

Fixed Size ◽

Mapping Algorithms

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A systematic generation of fault tolerant systolic arrays based on multiplicated multiple modular redundancy

Proceedings of ASP-DAC 95/CHDL 95/VLSI 95 with EDA Technofair ASPDAC-95 ◽

10.1109/aspdac.1995.486410 ◽

2002 ◽

Author(s):

M. Kaneko ◽

H. Miyauchi

Keyword(s):

Fault Tolerant ◽

Systolic Arrays ◽

Modular Redundancy

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Fault-Tolerant VLSI Systolic Arrays and Two-Level Pipelining

10.1117/12.936453 ◽

1983 ◽

Cited By ~ 5

Author(s):

H. T. Kung ◽

Monica S. Lam

Keyword(s):

Fault Tolerant ◽

Systolic Arrays

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Synthesis of orthogonal systolic arrays for fault-tolerant matrix multiplication

2010 27th International Conference on Microelectronics Proceedings ◽

10.1109/miel.2010.5490472 ◽

2010 ◽

Author(s):

M. K. Stojcev ◽

E. I. Milovanovic ◽

S. R. Markovic ◽

I. Z. Milovanovic

Keyword(s):

Fault Tolerant ◽

Matrix Multiplication ◽

Systolic Arrays

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Mapping algorithms to linear systolic arrays for wafer scale integration

[1989] Proceedings International Conference on Wafer Scale Integration ◽

10.1109/wafer.1989.47553 ◽

2003 ◽

Author(s):

V.K.P. Kumar ◽

Y.-C. Tsai

Keyword(s):

Systolic Arrays ◽

Mapping Algorithms ◽

Wafer Scale ◽

Wafer Scale Integration ◽

Scale Integration

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Fault-tolerant systolic arrays: An approach based upon residue arithmetic

1987 IEEE 8th Symposium on Computer Arithmetic (ARITH) ◽

10.1109/arith.1987.6158712 ◽

1987 ◽

Cited By ~ 7

Author(s):

Vincenzo Piuri

Keyword(s):

Fault Tolerant ◽

Systolic Arrays ◽

Residue Arithmetic

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Design techniques for fault-tolerant systolic arrays

The Journal of VLSI Signal Processing Systems for Signal Image and Video Technology ◽

10.1007/bf02106828 ◽

1995 ◽

Vol 11 (1-2) ◽

pp. 151-168 ◽

Cited By ~ 1

Author(s):

M. O. Esonu ◽

A. J. Al-Khalili ◽

S. Hariri ◽

D. Al-Khalili

Keyword(s):

Fault Tolerant ◽

Systolic Arrays ◽

Design Techniques

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