Design techniques for fault-tolerant systolic arrays

1995 ◽  
Vol 11 (1-2) ◽  
pp. 151-168 ◽  
Author(s):  
M. O. Esonu ◽  
A. J. Al-Khalili ◽  
S. Hariri ◽  
D. Al-Khalili
Keyword(s):  
Fault Tolerant ◽  
Systolic Arrays ◽  
Design Techniques

Restructuring for fault-tolerant systolic arrays

1989 ◽  
Vol 38 (2) ◽  
pp. 307-311 ◽  
Author(s):  
H.F. Li ◽  
R. Jayakumar ◽  
C. Lam
Keyword(s):  
Fault Tolerant ◽  
Systolic Arrays

scholarly journals SET and noise fault tolerant circuit design techniques: Application to 7nm FinFET

2014 ◽  
Vol 54 (4) ◽  
pp. 738-745 ◽  
Author(s):  
A. Calomarde ◽  
E. Amat ◽  
F. Moll ◽  
J. Vigara ◽  
A. Rubio
Keyword(s):  
Circuit Design ◽  
Fault Tolerant ◽  
Design Techniques

A Comparison of TMR With Alternative Fault-Tolerant Design Techniques for FPGAs

2007 ◽  
Vol 54 (6) ◽  
pp. 2065-2072 ◽  
Author(s):  
Keith S. Morgan ◽  
Daniel L. McMurtrey ◽  
Brian H. Pratt ◽  
Michael J. Wirthlin
Keyword(s):  
Fault Tolerant ◽  
Fault Tolerant Design ◽  
Design Techniques
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