Investigation and optimization of HfO2 gate dielectric on N-polar GaN: Impact of surface treatments, deposition, and annealing conditions

2021 ◽  
Vol 119 (4) ◽  
pp. 042901
Author(s):  
Subhajit Mohanty ◽  
Islam Sayed ◽  
Zhe (Ashley) Jian ◽  
Umesh Mishra ◽  
Elaheh Ahmadi
Keyword(s):  
Gate Dielectric ◽  
Surface Treatments ◽  
Annealing Conditions

Interface Quality and Electrical Performance of Low-Temperature Metal Organic Chemical Vapor Deposition Aluminum Oxide Thin Films for Advanced CMOS Gate Dielectric Applications

2002 ◽  
Vol 745 ◽  
Author(s):  
Spyridon Skordas ◽  
Filippos Papadatos ◽  
Steven Consiglio ◽  
Eric Eisenbraun ◽  
Alain Kaloyeros
Keyword(s):  
Dielectric Constant ◽  
Leakage Current ◽  
Gate Dielectric ◽  
Chemical Vapor ◽  
Oxide Semiconductor ◽  
Electrical Performance ◽  
Organic Chemical ◽  
Si Substrates ◽  
Annealing Conditions ◽  
Metal Organic

ABSTRACTIn this work, the electrical performance and interfacial characteristics of MOCVD-grown Al2O3 films are evaluated. Electrical characteristics (dielectric constant, leakage current) of as-deposited and annealed capacitor metal-oxide-semiconductor (MOS) stacks were determined using capacitance-voltage (C-V) and current-voltage (I-V) measurements. It was observed that the electrical properties were dependent upon specific annealing conditions, with an anneal in O2 followed by forming gas being superior with respect to leakage current, resulting in leakage characteristics superior to those of SiO2. All annealing conditions evaluated led to an increase in dielectric constant from 6.5 to 9.0–9.8. Also, Al2O3 growth and interfacial oxide growth characteristics on oxynitride/Si and Si substrates were evaluated and compared using spectroscopic ellipsometry. A parasitic oxide layer was observed to form on silicon during the initial stages of MOCVD Al2O3 growth, while a thin oxynitride layer deposited on Si prevented the growth of interfacial oxide.

Surface treatments on AlGaN/GaN heterostructures for gate dielectric Al2O3 thin films grown by Atomic Layer Deposition

2016 ◽  
Vol 617 ◽  
pp. 138-142 ◽  
Author(s):  
Raffaella Lo Nigro ◽  
Emanuela Schilirò ◽  
Giuseppe Greco ◽  
Patrick Fiorenza ◽  
Fabrizio Roccaforte
Keyword(s):  
Thin Films ◽  
Atomic Layer Deposition ◽  
Gate Dielectric ◽  
Atomic Layer ◽  
Surface Treatments ◽  
Layer Deposition

The Influence of Defects on Compatibility and Yield of the HfO2-PolySilicon Gate Stack for CMOS Integration

2002 ◽  
Vol 745 ◽  
Author(s):  
V. S. Kaushik ◽  
S. DeGendt ◽  
R. Carter ◽  
M. Claes ◽  
E. Rohr ◽  
...  
Keyword(s):  
Gate Dielectric ◽  
Defect Density ◽  
Dielectric Thickness ◽  
Gate Electrodes ◽  
Root Cause ◽  
Annealing Conditions ◽  
Polysilicon Gate ◽  
Defect Sites ◽  
Cmos Transistor ◽  
P Type

ABSTRACTHafnium-based dielectrics are under wide consideration for high-K gate dielectric applications. Since the gate electrode typically used in CMOS integration consists of polysilicon with n- or p-type dopants, compatibility of the HfO2layer with the polySi deposition and dopant activation steps is critical. Capacitors were fabricated with HfO2films deposited by ALD and MOCVD, and using polysilicon gate electrodes deposited by CVD processes. These devices showed leakage failures with yields that were observed to depend on the area, dielectric thickness and annealing conditions during the process. Investigation of the root cause of these leakage failures suggested that the leakage failures may be caused by a defect-related mechanism. The implication of this is that the leakage occurs at localized ‘defect’ sites rather than broadly through the HfO2layer. Emission microscopy analysis and physical characterization of the HfO2film were used to corroborate the proposed model. Defect density was observed to be strongly dependent on the processing of the dielectric film. In order to make Hf-based dielectric stacks compatible with polysilicon for conventional CMOS transistor integration with acceptable yield, further postdeposition treatment may be necessary to eliminate or cure the defects.

Alternative Gate Dielectrics with BST/TIO2/(Barrier Oxide) Stacked Structure

1998 ◽  
Vol 525 ◽  
Author(s):  
Yongjoo Jeon ◽  
Byoung Hun Lee ◽  
Keith Zawadzki ◽  
Wen-Jie Qi ◽  
Jack C. Lee
Keyword(s):  
Leakage Current ◽  
Barrier Layer ◽  
Gate Dielectric ◽  
Gate Dielectrics ◽  
Tunneling Current ◽  
Annealing Conditions ◽  
Higher Temperature ◽  
Direct Tunneling Current ◽  
Mis Capacitors

ABSTRACTBST/TiO2/(Barrier Layer) stacked dielectric structure has been proposed for ultra thin (<20Å) gate dielectric application to overcome the direct tunneling current problem of Si02. To characterize the alternative dielectrics, MIM and MIS capacitors were fabricated. TiO2 is believed to prevent BST and Si from reaction and interdiffusion while TiC2 itself is stable due to the strong binding energy. For better interfacial quality of TiO2/Si interface, proper barrier layer is needed between TiO2 and Si. Optimization of this barrier layer was performed by RTP grown N20 oxide and self-grown interfacial oxide layer with various annealing conditions. To monitor these barrier layers, TEM and electrical analysis were performed. From TEM observation, it was found that interfacial layer was formed in every sample whether it was intentionally grown or not. It was observed that the leakage current of Pt/TiO2/Si dramatically increased after 700'C or higher temperature annealing. This might be related to the transition of crystal structure of TiO2 from anatese to rutile at about 700°C[1]. It was also found that both Pt/BST/TiO2/Si and Pt/TiO2/Si showed lower leakage current compare to the conventional NO oxide at comparable equivalent SiO2 thickness. These results imply that these materials hold some promise as alternatives of pure SiO2 in very thin range.

The Influence of Defects on Compatibility and Yield of the HfO2-PolySilicon Gate Stack for CMOS Integration

2002 ◽  
Vol 747 ◽  
Author(s):  
V. S. Kaushik ◽  
S. DeGendt ◽  
R. Carter ◽  
M. Claes ◽  
E. Rohr ◽  
...  
Keyword(s):  
Gate Dielectric ◽  
Defect Density ◽  
Dielectric Thickness ◽  
Gate Electrodes ◽  
Root Cause ◽  
Annealing Conditions ◽  
Polysilicon Gate ◽  
Defect Sites ◽  
Cmos Transistor ◽  
P Type

ABSTRACTHafnium-based dielectrics are under wide consideration for high-K gate dielectric applications. Since the gate electrode typically used in CMOS integration consists of polysilicon with n- or p-type dopants, compatibility of the HfO2layer with the polySi deposition and dopant activation steps is critical. Capacitors were fabricated with HfO2films deposited by ALD and MOCVD, and using polysilicon gate electrodes deposited by CVD processes. These devices showed leakage failures with yields that were observed to depend on the area, dielectric thickness and annealing conditions during the process. Investigation of the root cause of these leakage failures suggested that the leakage failures may be caused by a defect-related mechanism. The implication of this is that the leakage occurs at localized ‘defect’ sites rather than broadly through the HfO2layer. Emission microscopy analysis and physical characterization of the HfO2film were used to corroborate the proposed model. Defect density was observed to be strongly dependent on the processing of the dielectric film. In order to make Hf-based dielectric stacks compatible with polysilicon for conventional CMOS transistor integration with acceptable yield, further postdeposition treatment may be necessary to eliminate or cure the defects.

High Mobility Pentacene Field Effect Transistors on Plastic

2005 ◽  
Vol 870 ◽  
Author(s):  
Siddharth Mohapatra ◽  
Michelle Grigas ◽  
Robert Wenz ◽  
Robert Rotzoll ◽  
Viorel Olariu ◽  
...  
Keyword(s):  
Electrical Properties ◽  
Gate Dielectric ◽  
Field Effect Transistors ◽  
High Mobility ◽  
Channel Length ◽  
Surface Cleaning ◽  
Surface Treatments ◽  
Gate Insulator ◽  
Bottom Contact ◽  
Active Layers

AbstractThis paper reports the electrical properties of thin-film transistors with pentacene active layers used in a bottom contact transistor geometry utilizing solution processed poly-4-vinylphenol (PVP) as the gate dielectric processed on a polyethylene napthalate (PEN) substrate. The transistors sometimes exhibit mobilities in excess of 1cm2/Vs. The effect of various surface treatments of the gate insulator, on the electrical properties of these transistors discussed. The development of photolithographically defined 2νm channel length bottom contact transistors is emphasized as the speed of circuit elements such as the rectifier scale inversely as the square of the channel length of the transistors. Surface cleaning and semiconductor deposition techniques that improve transistor characteristics and reduce hysteresis are evaluated and the variation of the ION/IOFF ratios with the different surface treatments is noted.

scholarly journals Application of Metal-Oxide-Semiconductor structures containing silicon nanocrystals in radiation dosimetry

Open Physics ◽  
2015 ◽  
Vol 13 (1) ◽  
Author(s):  
Diana Nesheva ◽  
Nikola Nedev ◽  
Mario Curiel ◽  
Valeri Dzhurkov ◽  
Abraham Arias ◽  
...  
Keyword(s):  
Metal Oxide ◽  
Silicon Nanocrystals ◽  
Radiation Dosimetry ◽  
Gate Dielectric ◽  
Gate Dielectrics ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Semiconductor Structures ◽  
Annealing Conditions ◽  
Silicon Structures

AbstractThis article makes a brief review of the most important results obtained by the authors and their collaborators during the last four years in the field of the development of metal-insulator-silicon structures with dielectric film containing silicon nanocrystals, which are suitable for applications in radiation dosimetry. The preparation of SiOx films is briefly discussed and the annealing conditions used for the growth of silicon nanocrystals are presented. A two-step annealing process for preparation of metal-oxide-semiconductor structures with three-layer gate dielectrics is described. Electron Microscopy investigations prove the Si nanocrystals growth, reveal the crystal spatial distribution in the gate dielectric and provide evidences for the formation of a top SiO2 layerwhen applying the two-step annealing. Two types of MOS structures with three region gate dielectricswere fabricated and characterized by high frequency capacitance/conductancevoltage (C/G-V) measurements. The effect of gamma and ultraviolet radiation on the flatband voltage of preliminary charged metal-oxide-semiconductor structures is investigated and discussed.

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