Charge trapping instabilities in amorphous silicon‐silicon nitride thin‐film transistors

1983 ◽  
Vol 43 (6) ◽  
pp. 597-599 ◽  
Author(s):  
M. J. Powell
Keyword(s):  
Thin Film ◽  
Silicon Nitride ◽  
Amorphous Silicon ◽  
Thin Film Transistors ◽  
Charge Trapping ◽  
Silicon Silicon

Charge trapping effects in amorphous silicon/silicon nitride thin film transistors

1987 ◽  
Vol 97-98 ◽  
pp. 903-906 ◽  
Author(s):  
A.R. Hepburn ◽  
C. Main ◽  
J.M. Marshall ◽  
C. van Berkel ◽  
M.J. Powell
Keyword(s):  
Thin Film ◽  
Silicon Nitride ◽  
Amorphous Silicon ◽  
Thin Film Transistors ◽  
Charge Trapping ◽  
Silicon Silicon ◽  
Trapping Effects

Amorphous silicon‐silicon nitride thin‐film transistors

1981 ◽  
Vol 38 (10) ◽  
pp. 794-796 ◽  
Author(s):  
M. J. Powell ◽  
B. C. Easton ◽  
O. F. Hill
Keyword(s):  
Thin Film ◽  
Silicon Nitride ◽  
Amorphous Silicon ◽  
Thin Film Transistors ◽  
Silicon Silicon

Threshold Voltage Shifts in Amorphous Silicon Thin Film Transistors under Bias Stress

1990 ◽  
Vol 192 ◽  
Author(s):  
Tetsu Ogawa ◽  
Sadayoshi Hotta ◽  
Horoyoshi Takezawa
Keyword(s):  
Thin Film ◽  
Temperature Dependence ◽  
Amorphous Silicon ◽  
Threshold Voltage ◽  
Thin Film Transistors ◽  
Charge Trapping ◽  
The Other ◽  
Time Dependent ◽  
Silicon Thin Film ◽  
Bias Stress

ABSTRACTThrough the time and temperature dependence measurements on threshold voltage shifts (Δ VT) in amorphous silicon thin film transistors, it has been found that two separate instability mechanisms exist; within short stress time ranges Δ Vτ increases as log t and this behavior corresponds to charge trapping in SiN. On the other hand, in long stress time ranges Δ VT increases as t t/4 and can be explained by time-dependent creation of trap in a-Si.

Reaction Processes for Low Temperature (<150°C) Plasma Enhanced Deposition of Hydrogenated Amorphous Silicon Thin-Film Transistors on Transparent Plastic Substrates

1998 ◽  
Vol 508 ◽  
Author(s):  
Gregory N. Parsons ◽  
Chien-Sheng Yang ◽  
Tonya M. Klein ◽  
Laura Smith
Keyword(s):  
Thin Film ◽  
Silicon Nitride ◽  
Low Temperature ◽  
Amorphous Silicon ◽  
Charge Trapping ◽  
Rf Plasma ◽  
Processing Temperature ◽  
Silicon Thin Film ◽  
Transparent Plastic ◽  
Plastic Substrates

AbstractThis article presents mechanisms for low temperature (<150°C) rf plasma enhanced chemical vapor deposition of silicon and silicon nitride thin films that lead to sufficient electronic quality for thin film transistor (TFT) fabrication and operation. For silicon deposition, hydrogen abstraction and etching, and silicon disproportionation reactions are identified that can lead to optimized hydrogen concentration and bonding environments at <150°C. Nitrogen dilution of SiH4/NH3 mixtures during silicon nitride deposition at low temperatures helps promote N-H bonding, leading to reduced charge trapping. Good quality amorphous silicon TFT's fabricated with a maximum processing temperature of 110 °C are demonstrated on flexible transparent plastic substrates. Transistors formed with the same process on glass and plastic show linear mobilities of 0.33 and 0.12 cm2/Vs, respectively, with ION/IOFF ratios > 106.

Material Properties Controlling the Performance of Amorphous Silicon Thin Film Transistors

1984 ◽  
Vol 33 ◽  
Author(s):  
M. J. Powell
Keyword(s):  
Thin Film ◽  
Silicon Nitride ◽  
Amorphous Silicon ◽  
Density Of States ◽  
Threshold Voltage ◽  
Material Properties ◽  
Thin Film Transistors ◽  
Gate Insulator ◽  
Dangling Bond ◽  
Silicon Thin Film

ABSTRACTAmorphous silicon thin film transistors have been fabricated with a number of different structures and materials. To date, the best performance is obtained with amorphous silicon - silicon nitride thin film transistors in the inverted staggered electrode structure, where the gate insulator and semiconductor are deposited sequentially by plasma enhanced chemical vapour deposition in the same growth apparatus.Localised electron states in the amorphous silicon are crucial in determining transistor performance. Conduction band states (Si-Si antibonding σ*) are broadened and localised in the amorphous network, and their energy distribution determines the field effect mobility. The silicon dangling bond defect is the most important deep localised state and their density determines the prethreshold current and hence the threshold voltage. The density of states is influenced by the gate insulator interface and there is probably a decreasing density of states away from this interface. The silicon dangling bond defect in the bulk amorphous silicon nitride also leads to a localised gap state, which is responsible for the observed threshold voltage instability.Other key material properties include the fixed charge densities associated with primary passivating layers placed on top of the amorphous silicon. The low value of the bulk density of states in the amorphous silicon layer increases the sensitivity of device characteristics to charge at the top interface.

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