Electrical properties of a unique solid array capacitor with 6 capacitance consisting of 4 electrodes and 3 organic dielectrics in single body

2018 ◽  
Author(s):  
Hwa-Sun Park ◽  
Young-Il Na ◽  
Ho-Joon Choi ◽  
Dae-Seok Seo ◽  
Su-Jeong Suh ◽  
...  
Keyword(s):  
Electrical Properties ◽  
Single Body ◽  
Organic Dielectrics

scholarly journals Electrical Properties of Horizontal Array Capacitor Using Composite Organic Dielectric Layer of Impregnated Glass-Fiber Epoxy

2020 ◽  
Vol 2020 ◽  
pp. 1-8
Author(s):  
Hwa-Sun Park ◽  
Young-Il Na ◽  
Sang-Min Lee ◽  
Su-Jeong Suh ◽  
Yong-Soo Oh ◽  
...  
Keyword(s):  
Electrical Properties ◽  
Glass Fiber ◽  
Dielectric Layer ◽  
Vertical Direction ◽  
Rate Of Change ◽  
Average Value ◽  
Single Body ◽  
Organic Solid ◽  
Organic Dielectric ◽  
Horizontal Array

We introduce a horizontal array capacitor with nine capacitances in a single body using an organic dielectric layer impregnated with glass fiber as a prepreg sheet. An organic solid horizontal array capacitor with a dielectric of prepreg materials of the epoxy type can implement the nine capacitances in a single body via a unique simple lamination and cutting process. We then investigate the basic electrical properties of a horizontal array capacitor. The organic solid array capacitors with five electrodes and four dielectrics are Cu/PPG layer/Cu/PPG layer/Cu/PPG layer/Cu/PPG layer/Cu with a horizontal array structure. The size of a completed array capacitor is 2.85 × 2.85 mm. The height of the fabricated array capacitor in the vertical direction is 0.5 mm, with nine capacitances possessing a series-type structure. The average capacitance value of C1, C2, C3, and C4 is 1.98 nF, and each tolerance has a value within 1% based on the average value. The temperature change rate in the capacitance maintains a nearly linear characteristic, but the rate of change tends to increase finely from 120°C or more. The capacitance values of C5, C6, and C7 with the parallel circuit were measured according to the voltage. Impedance and ESR (equivalent series resistor) of C1 were measured according to frequency and temperature.

In situ TEM measurements of the electrical properties of interface dislocations

1992 ◽  
Vol 50 (2) ◽  
pp. 1338-1339
Author(s):  
F. M. Ross ◽  
R. Hull ◽  
D. Bahnck ◽  
J. C. Bean ◽  
L. J. Peticolas ◽  
...  
Keyword(s):  
Electrical Properties ◽  
Electronic Device ◽  
In Situ Tem ◽  
Device Performance ◽  
Misfit Dislocations ◽  
Electrical Characteristics ◽  
Strained Layer ◽  
Transmission Electron ◽  
Interfacial Dislocations

We describe an investigation of the electrical properties of interfacial dislocations in strained layer heterostructures. We have been measuring both the structural and electrical characteristics of strained layer p-n junction diodes simultaneously in a transmission electron microscope, enabling us to correlate changes in the electrical characteristics of a device with the formation of dislocations.The presence of dislocations within an electronic device is known to degrade the device performance. This degradation is of increasing significance in the design and processing of novel strained layer devices which may require layer thicknesses above the critical thickness (hc), where it is energetically favourable for the layers to relax by the formation of misfit dislocations at the strained interfaces. In order to quantify how device performance is affected when relaxation occurs we have therefore been investigating the electrical properties of dislocations at the p-n junction in Si/GeSi diodes.

The morphologies and electrical properties of indium contacts on (100) cadmium telluride surfaces

1992 ◽  
Vol 50 (2) ◽  
pp. 1422-1423
Author(s):  
A.M. Letsoalo ◽  
M.E. Lee ◽  
E.O. de Neijs
Keyword(s):  
Electrical Properties ◽  
Cadmium Telluride ◽  
Methanol Solution ◽  
Electrical Characteristics ◽  
Metal Contacts ◽  
Deposition Technique ◽  
Interfacial Layers ◽  
Semiconductor Contacts ◽  
Grown Single Crystal ◽  
Diamond Abrasive

Semiconductor devices require metal contacts for efficient collection of electrical charge. The physics of these metal/semiconductor contacts assumes perfect, abrupt and continuous interfaces between the layers. However, in practice these layers are neither continuous nor abrupt due to poor nucleation conditions and the formation of interfacial layers. The effects of layer thickness, deposition rate and substrate stoichiometry have been previously reported. In this work we will compare the effects of a single deposition technique and multiple depositions on the morphology of indium layers grown on (100) CdTe substrates. The electrical characteristics and specific resistivities of the indium contacts were measured, and their relationships with indium layer morphologies were established.Semi-insulating (100) CdTe samples were cut from Bridgman grown single crystal ingots. The surface of the as-cut slices were mechanically polished using 5μm, 3μm, 1μm and 0,25μm diamond abrasive respectively. This was followed by two minutes immersion in a 5% bromine-methanol solution.

Formation of high temperature phase in flash-evaporated SnSe films

1990 ◽  
Vol 48 (4) ◽  
pp. 698-699
Author(s):  
J.P.S. Hanjra
Keyword(s):  
Thin Films ◽  
Electrical Properties ◽  
Energy Gap ◽  
Dominant Role ◽  
Fine Powder ◽  
High Temperature Phase ◽  
Temperature Phase ◽  
Water Mixture ◽  
Flash Evaporation ◽  
Photovoltaic Applications

Tin mono selenide (SnSe) with an energy gap of about 1 eV is a potential material for photovoltaic applications. Various authors have studied the structure, electronic and photoelectronic properties of thin films of SnSe grown by various deposition techniques. However, for practical photovoltaic junctions the electrical properties of SnSe films need improvement. We have carried out investigations into the properties of flash evaporated SnSe films. In this paper we report our results on the structure, which plays a dominant role on the electrical properties of thin films by TEM, SEM, and electron diffraction (ED).Thin films of SnSe were deposited by flash evaporation of SnSe fine powder prepared from high purity Sn and Se, onto glass, mica and KCl substrates in a vacuum of 2Ø micro Torr. A 15% HF + 2Ø% HNO3 solution was used to detach SnSe film from the glass and mica substrates whereas the film deposited on KCl substrate was floated over an ethanol water mixture by dissolution of KCl. The floating films were picked up on the grids for their EM analysis.

The electrical properties of germanium semiconductors at low temperatures

Physica ◽  
1954 ◽  
Vol 3 (7-12) ◽  
pp. 834-844 ◽  
Author(s):  
H FRITZSCHE ◽  
K LARKHOROVITZ
Keyword(s):  
Electrical Properties ◽  
Low Temperatures

Electrical Properties of Dislocations in Plastically Deformed Float Zone Silicon

1995 ◽  
Vol 5 (9) ◽  
pp. 1327-1336 ◽  
Author(s):  
J. J. Simon ◽  
E. Yakimov ◽  
M. Pasquinelli
Keyword(s):  
Electrical Properties ◽  
Float Zone

Electrical properties and corrosion of Bi-2223 coatings on silver wires directly synthetized from a Bi-2223 precursor or from a Bi-2223/Bi-2212 mixture

1998 ◽  
Vol 08 (PR1) ◽  
pp. Pr1-51-Pr1-55 ◽  
Author(s):  
C. Lamine ◽  
F. Ben Azouz ◽  
T. Badeche ◽  
O. Monnereau ◽  
M. Ben Salem ◽  
...  
Keyword(s):  
Electrical Properties
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