Electrical Properties of Dislocations in Plastically Deformed Float Zone Silicon

1995 ◽  
Vol 5 (9) ◽  
pp. 1327-1336 ◽  
Author(s):  
J. J. Simon ◽  
E. Yakimov ◽  
M. Pasquinelli
Keyword(s):  
Electrical Properties ◽  
Float Zone

In situ TEM measurements of the electrical properties of interface dislocations

1992 ◽  
Vol 50 (2) ◽  
pp. 1338-1339
Author(s):  
F. M. Ross ◽  
R. Hull ◽  
D. Bahnck ◽  
J. C. Bean ◽  
L. J. Peticolas ◽  
...  
Keyword(s):  
Electrical Properties ◽  
Electronic Device ◽  
In Situ Tem ◽  
Device Performance ◽  
Misfit Dislocations ◽  
Electrical Characteristics ◽  
Strained Layer ◽  
Transmission Electron ◽  
Interfacial Dislocations

We describe an investigation of the electrical properties of interfacial dislocations in strained layer heterostructures. We have been measuring both the structural and electrical characteristics of strained layer p-n junction diodes simultaneously in a transmission electron microscope, enabling us to correlate changes in the electrical characteristics of a device with the formation of dislocations.The presence of dislocations within an electronic device is known to degrade the device performance. This degradation is of increasing significance in the design and processing of novel strained layer devices which may require layer thicknesses above the critical thickness (hc), where it is energetically favourable for the layers to relax by the formation of misfit dislocations at the strained interfaces. In order to quantify how device performance is affected when relaxation occurs we have therefore been investigating the electrical properties of dislocations at the p-n junction in Si/GeSi diodes.

Examination of Extra Electron Diffraction Spots Observed in Deuterium-Irradiated Silicon by Using Parallel Electron Beam Illumination

1990 ◽  
Vol 48 (2) ◽  
pp. 490-491
Author(s):  
Ryuichiro Oshima ◽  
Shoichiro Honda ◽  
Tetsuo Tanabe
Keyword(s):  
Electron Microscopy ◽  
Transmission Electron Microscopy ◽  
Silicon Single Crystal ◽  
Mixed Solution ◽  
Parallel Beam ◽  
Defect Clusters ◽  
Float Zone ◽  
Transmission Electron ◽  
Extra Electron ◽  
Diffraction Patterns

In order to examine the origin of extra diffraction spots and streaks observed in selected area diffraction patterns of deuterium irradiated silicon, systematic diffraction experiments have been carried out by using parallel beam illumination.Disc specimens 3mm in diameter and 0.5mm thick were prepared from a float zone silicon single crystal(B doped, 7kΩm), and were chemically thinned in a mixed solution of nitric acid and hydrogen fluoride to make a small hole at the center for transmission electron microscopy. The pre-thinned samples were irradiated with deuterium ions at temperatures between 300-673K at 20keV to a dose of 1022ions/m2, and induced lattice defects were examined under a JEOL 200CX electron microscope operated at 160kV.No indication of formation of amorphous was obtained in the present experiments. Figure 1 shows an example of defects induced by irradiation at 300K with a dose of 2xl021ions/m2. A large number of defect clusters are seen in the micrograph.

The morphologies and electrical properties of indium contacts on (100) cadmium telluride surfaces

1992 ◽  
Vol 50 (2) ◽  
pp. 1422-1423
Author(s):  
A.M. Letsoalo ◽  
M.E. Lee ◽  
E.O. de Neijs
Keyword(s):  
Electrical Properties ◽  
Cadmium Telluride ◽  
Methanol Solution ◽  
Electrical Characteristics ◽  
Metal Contacts ◽  
Deposition Technique ◽  
Interfacial Layers ◽  
Semiconductor Contacts ◽  
Grown Single Crystal ◽  
Diamond Abrasive

Semiconductor devices require metal contacts for efficient collection of electrical charge. The physics of these metal/semiconductor contacts assumes perfect, abrupt and continuous interfaces between the layers. However, in practice these layers are neither continuous nor abrupt due to poor nucleation conditions and the formation of interfacial layers. The effects of layer thickness, deposition rate and substrate stoichiometry have been previously reported. In this work we will compare the effects of a single deposition technique and multiple depositions on the morphology of indium layers grown on (100) CdTe substrates. The electrical characteristics and specific resistivities of the indium contacts were measured, and their relationships with indium layer morphologies were established.Semi-insulating (100) CdTe samples were cut from Bridgman grown single crystal ingots. The surface of the as-cut slices were mechanically polished using 5μm, 3μm, 1μm and 0,25μm diamond abrasive respectively. This was followed by two minutes immersion in a 5% bromine-methanol solution.

Morphology and development of flow-pattern defect with extended nonagitated Secco etching

1994 ◽  
Vol 52 ◽  
pp. 868-869
Author(s):  
Y. Pan
Keyword(s):  
Flow Pattern ◽  
Silicon Crystal ◽  
Gate Oxide ◽  
Crystal Growth Rate ◽  
Etch Depth ◽  
Force Microscopy ◽  
Etch Pit ◽  
Float Zone ◽  
Atomic Force ◽  
Multiple Step

The D defect, which causes the degradation of gate oxide integrities (GOI), can be revealed by Secco etching as flow pattern defect (FPD) in both float zone (FZ) and Czochralski (Cz) silicon crystal or as crystal originated particles (COP) by a multiple-step SC-1 cleaning process. By decreasing the crystal growth rate or high temperature annealing, the FPD density can be reduced, while the D defectsize increased. During the etching, the FPD surface density and etch pit size (FPD #1) increased withthe etch depth, while the wedge shaped contours do not change their positions and curvatures (FIG.l).In this paper, with atomic force microscopy (AFM), a simple model for FPD morphology by non-crystallographic preferential etching, such as Secco etching, was established.One sample wafer (FPD #2) was Secco etched with surface removed by 4 μm (FIG.2). The cross section view shows the FPD has a circular saucer pit and the wedge contours are actually the side surfaces of a terrace structure with very small slopes. Note that the scale in z direction is purposely enhanced in the AFM images. The pit dimensions are listed in TABLE 1.

Formation of high temperature phase in flash-evaporated SnSe films

1990 ◽  
Vol 48 (4) ◽  
pp. 698-699
Author(s):  
J.P.S. Hanjra
Keyword(s):  
Thin Films ◽  
Electrical Properties ◽  
Energy Gap ◽  
Dominant Role ◽  
Fine Powder ◽  
High Temperature Phase ◽  
Temperature Phase ◽  
Water Mixture ◽  
Flash Evaporation ◽  
Photovoltaic Applications

Tin mono selenide (SnSe) with an energy gap of about 1 eV is a potential material for photovoltaic applications. Various authors have studied the structure, electronic and photoelectronic properties of thin films of SnSe grown by various deposition techniques. However, for practical photovoltaic junctions the electrical properties of SnSe films need improvement. We have carried out investigations into the properties of flash evaporated SnSe films. In this paper we report our results on the structure, which plays a dominant role on the electrical properties of thin films by TEM, SEM, and electron diffraction (ED).Thin films of SnSe were deposited by flash evaporation of SnSe fine powder prepared from high purity Sn and Se, onto glass, mica and KCl substrates in a vacuum of 2Ø micro Torr. A 15% HF + 2Ø% HNO3 solution was used to detach SnSe film from the glass and mica substrates whereas the film deposited on KCl substrate was floated over an ethanol water mixture by dissolution of KCl. The floating films were picked up on the grids for their EM analysis.

The electrical properties of germanium semiconductors at low temperatures

Physica ◽  
1954 ◽  
Vol 3 (7-12) ◽  
pp. 834-844 ◽  
Author(s):  
H FRITZSCHE ◽  
K LARKHOROVITZ
Keyword(s):  
Electrical Properties ◽  
Low Temperatures
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