Low-voltage high-speed programming/erasing floating-gate memory device with gate-all-around polycrystalline silicon nanowire

2013 ◽  
Vol 103 (15) ◽  
pp. 153102 ◽  
Author(s):  
Ko-Hui Lee ◽  
Jung-Ruey Tsai ◽  
Ruey-Dar Chang ◽  
Horng-Chih Lin ◽  
Tiao-Yuan Huang
Keyword(s):  
Polycrystalline Silicon ◽  
High Speed ◽  
Low Voltage ◽  
Silicon Nanowire ◽  
Memory Device ◽  
Floating Gate ◽  
Floating Gate Memory

MBE-grown Si and Si1−xGexquantum dots embedded within epitaxial Gd2O3on Si(111) substrate for floating gate memory device

2013 ◽  
Vol 24 (50) ◽  
pp. 505709 ◽  
Author(s):  
S Manna ◽  
R Aluguri ◽  
A Katiyar ◽  
S Das ◽  
A Laha ◽  
...  
Keyword(s):  
Memory Device ◽  
Floating Gate ◽  
Floating Gate Memory

Semiconductor Nanocrystal Floating-gate Memory Devices

2004 ◽  
Vol 830 ◽  
Author(s):  
P. Dimitrakis ◽  
P. Normand
Keyword(s):  
Low Voltage ◽  
Ion Beam ◽  
Low Energy ◽  
Floating Gate ◽  
Device Performance ◽  
Memory Devices ◽  
Research Directions ◽  
Semiconductor Nanocrystal ◽  
Floating Gate Memory ◽  
Attractive Option

ABSTRACTCurrent research directions and recent advances in the area of semiconductor nanocrystal floating-gate memory devices are herein reviewed. Particular attention is placed on the advantages, limitations and perspectives of some of the principal new alternatives suggested for improving device performance and reliability. The attractive option of generating Si nanocrystal memories by ion-beam-synthesis (IBS) is discussed with emphasis on the ultra-low-energy (ULE) regime. Pertinent issues related to the fabrication of low-voltage memory cells and the integration of the ULE-IBS technique in manufactory environment are discussed. The effect on device performance of parasitic transistors that form at the channel corner of shallow trench isolated transistors is described in details. It is shown that such parasitic transistors lead to a substantial degradation of the electrical properties of the intended devices and dominates the memory behavior of deep submicronic cells.

Vertically and Laterally Self-Aligned Double-Layer of Nanocrystals in Nanopatterned Dielectric Layer for Nanocrystal Floating Gate Memory Device

2019 ◽  
Vol 33 (9) ◽  
pp. 75-82 ◽  
Author(s):  
Quanli Hu ◽  
Tae-Kwang Eom ◽  
Soo-Hyun Kim ◽  
Hyung-Jun Kim ◽  
Hyun Ho Lee ◽  
...  
Keyword(s):  
Double Layer ◽  
Dielectric Layer ◽  
Memory Device ◽  
Floating Gate ◽  
Floating Gate Memory
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