Nucleation and propagation of voids in microbumps for 3 dimensional integrated circuits

2011 ◽  
Vol 99 (25) ◽  
pp. 251913 ◽  
Author(s):  
Hsueh-Hsien Hsu ◽  
Shin-Yi Huang ◽  
Tao-Chih Chang ◽  
Albert T. Wu
Keyword(s):  
Integrated Circuits ◽  
3 Dimensional

3D-IC Integration Using D2C or D2W Alignment Schemes Together with Local Oxide Reduction

2011 ◽  
Vol 2011 (DPC) ◽  
pp. 001291-001315
Author(s):  
Gilbert Lecarpentier ◽  
Jean-Stephane Mottet ◽  
Keith Cooper ◽  
Michael Stead
Keyword(s):  
Integrated Circuits ◽  
High Density ◽  
Oxide Reduction ◽  
3D Ic ◽  
3 Dimensional ◽  
Temperature Requirements

3-Dimensional interconnection of high density integrated circuits enables building devices with greater functionality with higher performances in a smaller space. This paper explores the chip-to-chip and chip-to-wafer alignment and the associated bonding techniques such as in-situ reflow or thermocompression with a local oxide reduction which contributes to higher yield together with reduction of the force or temperature requirements.

Measurement of stresses in Cu and Si around through-silicon via by synchrotron X-ray microdiffraction for 3-dimensional integrated circuits

2012 ◽  
Vol 52 (3) ◽  
pp. 530-533 ◽  
Author(s):  
A.S. Budiman ◽  
H.-A.-S. Shin ◽  
B.-J. Kim ◽  
S.-H. Hwang ◽  
H.-Y. Son ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Through Silicon Via ◽  
X Ray ◽  
3 Dimensional

scholarly journals 3D Spatial Layouts Using A-Teams

1998 ◽  
Author(s):  
Sanjay Sachdev ◽  
Christiaan J. J. Paredis ◽  
Satyandra K. Gupta ◽  
Sarosh N. Talukdar
Keyword(s):  
Integrated Circuits ◽  
Ad Hoc ◽  
Spatial Layout ◽  
New Agents ◽  
Agent Based ◽  
3 Dimensional ◽  
Task Requirements ◽  
Spatial Layouts ◽  
Traditional Approaches ◽  
Connection Cost

Abstract Spatial layout is the problem of arranging a set of components in an enclosure such that a set of objectives and constraints is satisfied. The constraints may include non-interference of objects, accessibility requirements and connection cost limits. Spatial layout problems are found primarily in the domains of electrical engineering and mechanical engineering in the design of integrated circuits and mechanical or electromechanical artifacts. Traditional approaches include ad-hoc (or specialized) heuristics, Genetic Algorithms and Simulated Annealing. The A-Teams approach provides a way of synergistically combining these approaches in a modular agent based fashion. A-Teams are also open to the addition of new agents. Modifications in the task requirements translate to modifications in the agent mix. In this paper we describe how modular A-Team based optimization can be used to solve 3 dimensional spatial layout problems.

Aerosol Jet Printer as an Alternative to Wire Bond and TSV Technology for 3D Interconnect Applications

2011 ◽  
Vol 2011 (DPC) ◽  
pp. 001250-001268
Author(s):  
Michael O'Reilly ◽  
Michael J. Renn ◽  
Stephen Barnes
Keyword(s):  
Aspect Ratio ◽  
Integrated Circuits ◽  
High Performance ◽  
3 Dimensional ◽  
Wire Bond ◽  
Printing System ◽  
Performance System ◽  
Definition Of ◽  
Working Distance ◽  
Nanoparticle Ink

Optomec's Aerosol Jet print platform provides an evolutionary alternative to both wire bond and TSV technology, providing high density 3-dimensional interconnect capabilities which enable multi-functional integrated circuits to be stacked and vertically interconnected in high performance System-in-Package (SiP) solutions. The die stacks can include 8 or more die, with a total stack height of ~ 1 mm. The printing system has a working distance of several mm which means that no Z-height adjustments are required for the interconnect printing. Closely coupled pneumatic atomizers with multiplexed print nozzles are used to achieve production throughput of greater than 15,000 interconnects per hour. The Aerosol Jet deposits silver nanoparticle ink connections on staggered multi-chip die stacks. High aspect ratio interconnects with <30-micron line width and 6-micron line heights have been demonstrated at sub 60-micron pitches with resistivity <1x10−7 ohm*m. Pre-production yields exceeding 80% have been consistently realized. This paper will be further expanded to include pre-production qualification results, final production packaging, and further definition of the Aerosol Jet print platform integrated within a high throughput, manufacturing ready automation solution.

Aluminum thermomigration technology for 3-dimensional integrated circuits

1981 ◽  
Author(s):  
J.Y.M. Lee ◽  
R.H. Brown ◽  
R.D. Etchells ◽  
J. Grinberg ◽  
G.R. Nudd ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
3 Dimensional
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