Positive charge generation in metal‐oxide‐semiconductor capacitors

1991 ◽  
Vol 69 (4) ◽  
pp. 2512-2521 ◽  
Author(s):  
L. P. Trombetta ◽  
F. J. Feigl ◽  
R. J. Zeto
Keyword(s):  
Metal Oxide ◽  
Positive Charge ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Charge Generation

Charge generation in metal-oxide-semiconductor capacitors during Fowler-Nordheim stress

1994 ◽  
Vol 4 (6) ◽  
pp. 1045-1051 ◽  
Author(s):  
S. Elrharbi ◽  
M. Jourdain ◽  
A. Meinertzhagen ◽  
A. El-Hdiy ◽  
C. Petit
Keyword(s):  
Metal Oxide ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Charge Generation

On the positive charge and interface states in metal‐oxide‐semiconductor capacitors

1996 ◽  
Vol 80 (1) ◽  
pp. 271-277 ◽  
Author(s):  
A. Meinertzhagen ◽  
C. Petit ◽  
G. Yard ◽  
M. Jourdain ◽  
A. El Hdiy
Keyword(s):  
Metal Oxide ◽  
Positive Charge ◽  
Interface States ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor

Suppression of Timing Variations due to Random Dopant Fluctuation by Back-Gate Bias in a Nanometer CMOS Inverter

2020 ◽  
Vol 13 ◽  
Author(s):  
Kai Zhang ◽  
Weifeng Lü ◽  
Peng Si ◽  
Zhifeng Zhao ◽  
Tianyu Yu
Keyword(s):  
Monte Carlo ◽  
Integrated Circuits ◽  
Metal Oxide ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Gate Bias ◽  
Cmos Inverter ◽  
Back Gate ◽  
Random Dopant Fluctuation ◽  
Random Dopant

Background: In state-of-the-art nanometer metal-oxide-semiconductor-field-effect- transistors (MOSFETs), optimization of timing characteristic is one of the major concerns in the design of modern digital integrated circuits. Objective: This study proposes an effective back-gate-biasing technique to comprehensively investigate the timing and its variation due to random dopant fluctuation (RDF) employing Monte Carlo methodology. Methods: To analyze RDF-induced timing variation in a 22-nm complementary metal-oxide semiconductor (CMOS) inverter, an ensemble of 1000 different samples of channel-doping for negative metal-oxide semiconductor (NMOS) and positive metal-oxide semiconductor (PMOS) was reproduced and the input/output curves were measured. Since back-gate bias is technology dependent, we present in parallel results with and without VBG. Results: It is found that the suppression of RDF-induced timing variations can be achieved by appropriately adopting back-gate voltage (VBG) through measurements and detailed Monte Carlo simulations. Consequently, the timing parameters and their variations are reduced and, moreover, that they are also insensitive to channel doping with back-gate bias. Conclusion: Circuit designers can appropriately use back-gate bias to minimize timing variations and improve the performance of CMOS integrated circuits.

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