Fermi level pinning by defects in HfO2-metal gate stacks

2007 ◽  
Vol 91 (13) ◽  
pp. 132912 ◽  
Author(s):  
J. Robertson ◽  
O. Sharia ◽  
A. A. Demkov
2004 ◽  
Vol 811 ◽  
Author(s):  
Jamie Schaeffer ◽  
Sri Samavedam ◽  
Leonardo Fonseca ◽  
Cristiano Capasso ◽  
Olubunmi Adetutu ◽  
...  

ABSTRACTAs traditional poly-silicon gated MOSFET devices scale, the additional series capacitance due to poly-silicon depletion becomes an increasingly large fraction of the total gate capacitance, excessive boron penetration causes threshold voltage shifts, and the gate resistance is elevated. To solve these problems and continue aggressive device scaling we are studying metal electrodes with suitable work-functions and sufficient physical and electrical stability. Our studies of metal gates on HfO2 indicate that excessive inter-diffusion, inadequate phase stability, and interfacial reactions are mechanisms of failure at source drain activation temperatures that must be considered during the electrode selection process. Understanding the physical properties of the metal gate – HfO2 interface is critical to understanding the electrical behavior of MOS devices. Of particular interest is Fermi level pinning, a phenomenon that occurs at metal – dielectric interfaces which causes undesirable shifts in the effective metal work function. The magnitude of Fermi level pinning on HfO2 electrodes is studied with Pt and LaB6 electrodes. In addition, the intrinsic and extrinsic contributions to Fermi level pinning of platinum electrodes on HfO2 gate dielectrics are investigated by examining the impact of oxygen and forming gas anneals on the work function of platinum-HfO2-silicon capacitors. The presence of interfacial oxygen vacancies or Pt-Hf bonds is believed to be responsible for a degree of pinning that is stronger than predicted from the MIGS model alone. Interface chemistry and defects influence the effective metal work function.


2008 ◽  
Vol 92 (13) ◽  
pp. 132911 ◽  
Author(s):  
Peter Broqvist ◽  
Audrius Alkauskas ◽  
Alfredo Pasquarello

2009 ◽  
Vol 145-146 ◽  
pp. 215-218
Author(s):  
Masayuki Wada ◽  
Sylvain Garaud ◽  
I. Ferain ◽  
Nadine Collaert ◽  
Kenichi Sano ◽  
...  

High-k gate dielectrics (HK), such as HfO2 or HfSiON, are being considered as the gate dielectric option for the 45nm node and beyond. In order to alleviate the Fermi-level pinning issue and to enhance the CET (Capacitive Effective Thickness) by generating the depletion layer in poly-Silicon gate, metal gate electrodes with proper work functions (WF) have to be used on the high-k dielectrics.


2019 ◽  
Vol 11 (4) ◽  
pp. 169-180
Author(s):  
Masaru Kadoshima ◽  
Yoshihiro Sugita ◽  
Kenji Shiraishi ◽  
Heiji Watanabe ◽  
Akio Ohta ◽  
...  

Sign in / Sign up

Export Citation Format

Share Document