Improvement in Fermi-Level Pinning of p-MOS Metal Gate Electrodes on HfSiON by Employing Ru Gate Electrodes

2019 ◽  
Vol 11 (4) ◽  
pp. 169-180
Author(s):  
Masaru Kadoshima ◽  
Yoshihiro Sugita ◽  
Kenji Shiraishi ◽  
Heiji Watanabe ◽  
Akio Ohta ◽  
...  
2009 ◽  
Vol 145-146 ◽  
pp. 215-218
Author(s):  
Masayuki Wada ◽  
Sylvain Garaud ◽  
I. Ferain ◽  
Nadine Collaert ◽  
Kenichi Sano ◽  
...  

High-k gate dielectrics (HK), such as HfO2 or HfSiON, are being considered as the gate dielectric option for the 45nm node and beyond. In order to alleviate the Fermi-level pinning issue and to enhance the CET (Capacitive Effective Thickness) by generating the depletion layer in poly-Silicon gate, metal gate electrodes with proper work functions (WF) have to be used on the high-k dielectrics.


2004 ◽  
Vol 241 (10) ◽  
pp. 2253-2267 ◽  
Author(s):  
Zhiqiang Chen ◽  
Veena Misra ◽  
Ryan P. Haggerty ◽  
Susanne Stemmer

2007 ◽  
Vol 91 (13) ◽  
pp. 132912 ◽  
Author(s):  
J. Robertson ◽  
O. Sharia ◽  
A. A. Demkov

2020 ◽  
Vol 67 (4) ◽  
pp. 1730-1736
Author(s):  
Hongpeng Zhang ◽  
Lei Yuan ◽  
Xiaoyan Tang ◽  
Jichao Hu ◽  
Jianwu Sun ◽  
...  

2007 ◽  
Vol 102 (7) ◽  
pp. 074511 ◽  
Author(s):  
J. K. Schaeffer ◽  
D. C. Gilmer ◽  
S. Samavedam ◽  
M. Raymond ◽  
A. Haggag ◽  
...  

2002 ◽  
Vol 81 (22) ◽  
pp. 4192-4194 ◽  
Author(s):  
Tae-Ho Cha ◽  
Dae-Gyu Park ◽  
Tae-Kyun Kim ◽  
Se-Aug Jang ◽  
In-Seok Yeo ◽  
...  

2006 ◽  
Vol 27 (3) ◽  
pp. 148-150 ◽  
Author(s):  
Chin-Lung Cheng ◽  
Kuei-Shu Chang-Liao ◽  
Tzu-Chen Wang ◽  
Tien-Ko Wang ◽  
Howard Chih-Hao Wang

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