Electrical study of ferromagnet-oxide-semiconductor diode for a magnetic memory device integrated on silicon

2007 ◽  
Vol 90 (19) ◽  
pp. 192508 ◽  
Author(s):  
M. Kanoun ◽  
R. Benabderrahmane ◽  
C. Duluard ◽  
C. Baraduc ◽  
N. Bruyant ◽  
...  
Keyword(s):  
Memory Device ◽  
Oxide Semiconductor ◽  
Semiconductor Diode ◽  
Magnetic Memory ◽  
Electrical Study

scholarly journals Nb2O5 and Ti-Doped Nb2O5 Charge Trapping Nano-Layers Applied in Flash Memory

Nanomaterials ◽  
2018 ◽  
Vol 8 (10) ◽  
pp. 799 ◽  
Author(s):  
Jer Wang ◽  
Chyuan Kao ◽  
Chien Wu ◽  
Chun Lin ◽  
Chih Lin
Keyword(s):  
Flash Memory ◽  
Charge Trapping ◽  
Memory Device ◽  
Dielectric Constants ◽  
Oxide Semiconductor ◽  
Flat Band ◽  
Hysteresis Curve ◽  
Band Shift ◽  
K Value ◽  
High K

High-k material charge trapping nano-layers in flash memory applications have faster program/erase speeds and better data retention because of larger conduction band offsets and higher dielectric constants. In addition, Ti-doped high-k materials can improve memory device performance, such as leakage current reduction, k-value enhancement, and breakdown voltage increase. In this study, the structural and electrical properties of different annealing temperatures on the Nb2O5 and Ti-doped Nb2O5(TiNb2O7) materials used as charge-trapping nano-layers in metal-oxide-high k-oxide-semiconductor (MOHOS)-type memory were investigated using X-ray diffraction (XRD) and atomic force microscopy (AFM). Analysis of the C-V hysteresis curve shows that the flat-band shift (∆VFB) window of the TiNb2O7 charge-trapping nano-layer in a memory device can reach as high as 6.06 V. The larger memory window of the TiNb2O7 nano-layer is because of a better electrical and structural performance, compared to the Nb2O5 nano-layer.

Organic/Inorganic Hybrid-Type Nonvolatile Memory Thin-Film Transistor on Plastic Substrate below 150°C

2011 ◽  
Vol 1287 ◽  
Author(s):  
Sung-Min Yoon ◽  
Shinhyuk Yang ◽  
Soon-Won Jung ◽  
Sang-Hee Ko Park ◽  
Chun-Won Byun ◽  
...  
Keyword(s):  
Flexible Electronics ◽  
Nonvolatile Memory ◽  
Vinylidene Fluoride ◽  
Thin Film Transistor ◽  
Memory Device ◽  
Gate Insulator ◽  
Oxide Semiconductor ◽  
Plastic Substrate ◽  
Inorganic Hybrid ◽  
Hybrid Type

ABSTRACTAn organic/inorganic hybrid-type nonvolatile memory TFT was proposed as a core device for the future flexible electronics. The structural feature of this memory TFT was that a ferroelectric copolymer and an oxide semiconductor layers were employed as a gate insulator and an active channel, respectively. The memory TFT with the structure of Au/poly(vinylidene fluoride-trifluoroethylene)/Al2O3/ZnO/Ti/Au/Ti/poly(ethylene naphthalate) could be successfully fabricated at the process temperature of below 150°C. It was confirmed that the TFT well operated as a memory device even under the bending situations.

Negative Differential Resistance Characteristics of Silicon Nanocrystal Memory

2000 ◽  
Vol 609 ◽  
Author(s):  
Seung Jae Baik ◽  
Koeng Su Lim
Keyword(s):  
Quantum Dot ◽  
Negative Differential Resistance ◽  
Chemical Vapor ◽  
Differential Resistance ◽  
Memory Device ◽  
Oxide Semiconductor ◽  
Si Quantum Dot ◽  
Charge Tunneling ◽  
Nanocrystal Memory ◽  
Average Size

ABSTRACTTwo-dimensional (2D) Si quantum dot array was fabricated by oxidation of microcrystalline Si film deposited by photo chemical vapor deposition (photo-CVD). Average size of Si quantum dot was estimated to be 2.4nm and dot density 7 ∼ 8 ×1011 cm−2. Nanocrystal memory device with this 2D quantum dot array demonstrated negative differential resistance characteristics and single charge tunneling phenomena, which was observed as stepwise decrease of gate transconductance. Interface states at the oxidized surface of quantum dots were assumed to explain temperature dependence characteristics. This new process is adequate for functional device application of nanocrystal metal-oxide-semiconductor (MOS) memory.

C‐Vcharacteristics of SiC metal‐oxide‐semiconductor diode with a thermally grown SiO2layer

1981 ◽  
Vol 39 (1) ◽  
pp. 89-90 ◽  
Author(s):  
Akira Suzuki ◽  
Kazunobu Mameno ◽  
Nobuyuki Furui ◽  
Hiroyuki Matsunami
Keyword(s):  
Metal Oxide ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Semiconductor Diode ◽  
Thermally Grown

Tunneling transport properties for metal-oxide-semiconductor diode consisting of ferromagnetic ZnMnO nanocrystals

2010 ◽  
Vol 97 (18) ◽  
pp. 182103 ◽  
Author(s):  
Sejoon Lee ◽  
Youngmin Lee ◽  
Yoon Shon ◽  
Deuk Young Kim ◽  
Tae Won Kang
Keyword(s):  
Metal Oxide ◽  
Transport Properties ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Semiconductor Diode ◽  
Tunneling Transport

Electrical Characterization of GaN Metal Oxide Semiconductor Diode using Sc2O3 as the Gate Oxide

2001 ◽  
Vol 693 ◽  
Author(s):  
R. Mehandru ◽  
B.P. Gila ◽  
J. Kim ◽  
J.W. Johnson ◽  
K.P. Lee ◽  
...  
Keyword(s):  
Metal Oxide ◽  
Inductively Coupled Plasma ◽  
Electron Cyclotron Resonance ◽  
Gate Oxide ◽  
Metal Oxide Semiconductor ◽  
Trap Density ◽  
Oxide Semiconductor ◽  
Semiconductor Diode ◽  
Interface Trap Density ◽  
Interface Trap

AbstractGaN metal oxide semiconductor diodes were demonstrated utilizing Sc2O3 as the gate oxide. Sc2O3 was grown at 100°C on MOCVD grown n-GaN layers in a molecular beam epitaxy (MBE) system, using a scandium elemental source and an Electron Cyclotron Resonance (ECR) oxygen plasma. Ar/Cl2 based discharges was used to remove Sc2O3, in order to expose the underlying n-GaN for ohmic metal deposition in an Inductively Coupled Plasma system. Electron beam deposited Ti/Al/Pt/Au and Pt/Au were utilized as ohmic and gate metallizations, respectively. An interface trap density of 5 × 1011 eV-1cm-2was obtained with the Terman method. Conductance-voltage measurements were also used to estimate the interface trap density and a slightly higher number was obtained as compared to the Terman method. Results of capacitance measurements at elevated temperature (up to 300°C) indicated the presence of deep states near the interface.

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