Electrical characterization of Fermi level pinning in metal/3,4,9,10 perylenetetracarboxylic dianhydride interfaces

2006 ◽  
Vol 89 (22) ◽  
pp. 222114 ◽  
Author(s):  
Ruchi Agrawal ◽  
Subhasis Ghosh
Keyword(s):  
Fermi Level ◽  
Electrical Characterization ◽  
Fermi Level Pinning

Characterization of SiGeC Using Pt(SiGeC) Silicide Schottky Contacts

1998 ◽  
Vol 533 ◽  
Author(s):  
Jeff J. Peterson ◽  
Charles E. Hunt ◽  
McDonald Robinson ◽  
Robin SCott
Keyword(s):  
Fermi Level ◽  
Conduction Band ◽  
Electrical Characterization ◽  
Schottky Contacts ◽  
Epitaxial Layers ◽  
Fermi Level Pinning ◽  
Barrier Heights ◽  
Xrd Studies ◽  
P Type

AbstractMaterial and electrical characterization of n-type and p-type Si1-x-yGex Cy epitaxial layers on Si(100) was performed using silicided platinum Schottky contacts. XRD studies show Pt silcidation of SiGeC proceeds from non-reacted Pt to Pt2(SiGeC) and completes with the Pt(SiGeC) phase similar to Pt/Si silicides, but Pt silicide reactions with SiGeC are shown to require higher temperatures than Pt reactions with Si. Electrical characterization of Pt(SiGeC) contacts to n-type Sil1-x-yGexCx/Si shows rectifying behavior with constant barrier heights of 0.67eV independent of composition, indicating Fermi level pinning relative to the SiGeC conduction band is occurring. Pt(SiGeC) contacts to p-type Si1-x-yGexCy/Si are also rectifying with barrier heights that track the variation of the SiGeC energy bandgap.

Contactless Electromodulation Characterization of Compound Semiconductor Surfaces and Device Structures

1993 ◽  
Vol 324 ◽  
Author(s):  
J.M. Woodall
Keyword(s):  
Fermi Level ◽  
Electric Fields ◽  
Growth Conditions ◽  
Compound Semiconductor ◽  
Conduction Band Edge ◽  
Semiconductor Surfaces ◽  
Air Exposure ◽  
Fermi Level Pinning ◽  
Characterization Of Properties

AbstractThis paper will review the use of contactless electromodulation methods, such as photoreflectance (PR) and contactless electroreflectance (CER), to characterize the electronic properties of compound semiconductor surfaces exposed to different growth and post-growth conditions. Also the characterization of properties critical to device performance can be evaluated. For example, using PR and CER it has been found that there is a lower density of surface hole traps than electron traps in certain as-grown MBE (001) GaAs samples and that this condition persists even after air exposure. This behaviour is in contrast to other samples, including both bulk and MBE grown (001) surfaces in which the Fermi level is pinned mid-gap for both n- and p-type structures. We also have observed that Ar+ bombardment under UHV conditions results in Fermi level pinning close to the conduction band edge and that thermal annealing restores mid-gap pinning. Finally, using PR we are able to characterize the electric fields and associated doping levels in the emitter and collector regions of heterojunction bipolar transistor structures (fabricated from III-V materials), thus demonstrating the ability to perform inprocess evaluation of important device parameters.

Characterization of Cleaved GaAs(110) with a Scanning Photoemission Microscope Capable of Submicron Resolution

1993 ◽  
Vol 307 ◽  
Author(s):  
A. K. Ray-Chaudhuri ◽  
W. Ng ◽  
S. Liang ◽  
S. Singh ◽  
H. Solak ◽  
...  
Keyword(s):  
Fermi Level ◽  
Spatial Resolution ◽  
Spatial Extent ◽  
Kelvin Probe ◽  
Fermi Level Pinning ◽  
Contrast Mechanism ◽  
Cleavage Step ◽  
Step Over ◽  
Monolayer Coverage

ABSTRACTWe have utilized a scanning photoemission spectromicroscope with sub-micron spatial resolution to observe microscopic Fermi level pinning on the cleaved GaAs(110) surface. We present micrographs which identify pinning that is highly localized to the vicinity of a single linear cleavage step. This extends previous work utilizing scanning Kelvin probe and imaging photoelectron microscopy conducted at lower spatial resolution. A sub-monolayer coverage of In uniformly pins the surface, thus allowing us to observe only the image contrast mechanism resulting from topography. From this one can determine the spatial extent of defects near a cleavage step. Initial observations indicate that Fermi level pinning can extend from a cleavage step over the range of 2 μm. This indicates the additional presence of defects at the adjacent surfaces of the step.

Structural and Electrical Characterization of Shaped Beam Laser Recrystallized Polysilicon on Amorphous Substrates

1981 ◽  
Vol 4 ◽  
Author(s):  
T. J. Stultz ◽  
J. F. Gibbons
Keyword(s):  
Grain Size ◽  
Electrical Characterization ◽  
Grain Structure ◽  
Electrical Characteristics ◽  
Shaped Beam ◽  
Beam Laser ◽  
Cw Laser ◽  
Amorphous Substrates ◽  
Circular Beam

ABSTRACTStructural and electrical characterization of laser recrystallized LPCVD silicon films on amorphous substrates using a shaped cw laser beam have been performed. In comparing the results to data obtained using a circular beam, it was found that a significant increase in grain size can be achieved and that the surface morphology of the shaped beam recrystallized material was much smoother. It was also found that whereas circular beam recrystallized material has a random grain structure, shaped beam material is highly oriented with a <100> texture. Finally the electrical characteristics of the recrystallized film were very good when measured in directions parallel to the grain boundaries.

Vapor Deposition Polymerization and Electrical Characterization of TPD Thin Films

2011 ◽  
Vol E94-C (2) ◽  
pp. 157-163 ◽  
Author(s):  
Masakazu MUROYAMA ◽  
Ayako TAJIRI ◽  
Kyoko ICHIDA ◽  
Seiji YOKOKURA ◽  
Kuniaki TANAKA ◽  
...  
Keyword(s):  
Thin Films ◽  
Vapor Deposition ◽  
Electrical Characterization

Electrical Characterization of Different Failure Modes in Sub-100 nm Devices Using Nanoprobing Technique

2009 ◽  
Author(s):  
E. Hendarto ◽  
S.L. Toh ◽  
J. Sudijono ◽  
P.K. Tan ◽  
H. Tan ◽  
...  
Keyword(s):  
Electron Microscope ◽  
Focused Ion Beam ◽  
Failure Modes ◽  
Ion Beam ◽  
Electrical Characterization ◽  
Nickel Silicide ◽  
Fault Isolation ◽  
Technology Nodes ◽  
Scanning Electron

Abstract The scanning electron microscope (SEM) based nanoprobing technique has established itself as an indispensable failure analysis (FA) technique as technology nodes continue to shrink according to Moore's Law. Although it has its share of disadvantages, SEM-based nanoprobing is often preferred because of its advantages over other FA techniques such as focused ion beam in fault isolation. This paper presents the effectiveness of the nanoprobing technique in isolating nanoscale defects in three different cases in sub-100 nm devices: soft-fail defect caused by asymmetrical nickel silicide (NiSi) formation, hard-fail defect caused by abnormal NiSi formation leading to contact-poly short, and isolation of resistive contact in a large electrical test structure. Results suggest that the SEM based nanoprobing technique is particularly useful in identifying causes of soft-fails and plays a very important role in investigating the cause of hard-fails and improving device yield.

Case Studies in Atomic Force Probe Analysis

2006 ◽  
Author(s):  
Randal Mulder ◽  
Sam Subramanian ◽  
Tony Chrastecky
Keyword(s):  
Failure Analysis ◽  
Case Studies ◽  
Light Emission ◽  
Electrical Characterization ◽  
Logic Circuits ◽  
Contrast Imaging ◽  
Atomic Force ◽  
Measuring Surface ◽  
Analysis Environment

Abstract The use of atomic force probe (AFP) analysis in the analysis of semiconductor devices is expanding from its initial purpose of solely characterizing CMOS transistors at the contact level with a parametric analyzer. Other uses found for the AFP include the full electrical characterization of failing SRAM bit cells, current contrast imaging of SOI transistors, measuring surface roughness, the probing of metallization layers to measure leakages, and use with other tools, such as light emission, to quickly localize and identify defects in logic circuits. This paper presents several case studies in regards to these activities and their results. These case studies demonstrate the versatility of the AFP. The needs and demands of the failure analysis environment have quickly expanded its use. These expanded capabilities make the AFP more valuable for the failure analysis community.

Analysis of an Anomalous CMOS Transistor Exhibiting Drain to Source Leakage—Its Model and Cause

2014 ◽  
Author(s):  
Yuk L. Tsang ◽  
Alex VanVianen ◽  
Xiang D. Wang ◽  
N. David Theodore
Keyword(s):  
Threshold Voltage ◽  
Crystalline Silicon ◽  
Electrical Characterization ◽  
Visual Defect ◽  
Scanning Capacitance Microscopy ◽  
Device Model ◽  
Graphical Simulation ◽  
Cmos Transistor

Abstract In this paper, we report a device model that has successfully described the characteristics of an anomalous CMOS NFET and led to the identification of a non-visual defect. The model was based on detailed electrical characterization of a transistor exhibiting a threshold voltage (Vt) of about 120mv lower than normal and also exhibiting source to drain leakage. Using a simple graphical simulation, we predicted that the anomalous device was a transistor in parallel with a resistor. It was proposed that the resistor was due to a counter doping defect. This was confirmed using Scanning Capacitance Microscopy (SCM). The dopant defect was shown by TEM imaging to be caused by a crystalline silicon dislocation.

Analysis of an Anomalous Transistor Exhibiting Dual-Vt Characteristics and Its Cause in a 90nm Node CMOS Technology

2012 ◽  
Author(s):  
Yuk L. Tsang ◽  
Xiang D. Wang ◽  
Reyhan Ricklefs ◽  
Jason Goertz
Keyword(s):  
Threshold Voltage ◽  
Electrical Characterization ◽  
Cmos Technology ◽  
Short Channel ◽  
Visual Defect ◽  
Subthreshold Region ◽  
Short Channel Effect ◽  
Channel Effect ◽  
Transistor Model

Abstract In this paper, we report a transistor model that has successfully led to the identification of a non visual defect. This model was based on detailed electrical characterization of a MOS NFET exhibiting a threshold voltage (Vt) of just about 40mv lower than normal. This small Vt delta was based on standard graphical extrapolation method in the usual linear Id-Vg plots. We observed, using a semilog plot, two slopes in the Id-Vg curves with Vt delta magnified significantly in the subthreshold region. The two slopes were attributed to two transistors in parallel with different Vts. We further found that one of the parallel transistors had short channel effect due to a punch-through mechanism. It was proposed and ultimately confirmed the cause was due to a dopant defect using scanning capacitance microscopy (SCM) technique.

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