scholarly journals Theoretical investigation of surface roughness scattering in silicon nanowire transistors

2005 ◽  
Vol 87 (4) ◽  
pp. 043101 ◽  
Author(s):  
Jing Wang ◽  
Eric Polizzi ◽  
Avik Ghosh ◽  
Supriyo Datta ◽  
Mark Lundstrom
Keyword(s):  
Surface Roughness ◽  
Theoretical Investigation ◽  
Silicon Nanowire ◽  
Nanowire Transistors ◽  
Surface Roughness Scattering

Low-temperature operation of junctionless nanowire transistors: Less surface roughness scattering effects and dominant scattering mechanisms

2014 ◽  
Vol 105 (26) ◽  
pp. 263505 ◽  
Author(s):  
Dae-Young Jeon ◽  
So Jeong Park ◽  
Mireille Mouis ◽  
Sylvain Barraud ◽  
Gyu-Tae Kim ◽  
...  
Keyword(s):  
Surface Roughness ◽  
Low Temperature ◽  
Nanowire Transistors ◽  
Scattering Mechanisms ◽  
Surface Roughness Scattering ◽  
Scattering Effects

Calibration of Mobility and Interface Trap Parameters for High Temperature TCAD Simulation of 4H-SiC VDMOSFETs

2012 ◽  
Vol 717-720 ◽  
pp. 1101-1104 ◽  
Author(s):  
M.G. Jaikumar ◽  
Shreepad Karmalkar
Keyword(s):  
Surface Roughness ◽  
Measured Data ◽  
Interface Trap Density ◽  
Interface Trap ◽  
Material Parameters ◽  
Velocity Saturation ◽  
Physical Mechanisms ◽  
Surface Roughness Scattering ◽  
Wide Range ◽  
Tcad Simulation

4H-Silicon Carbide VDMOSFET is simulated using the Sentaurus TCAD package of Synopsys. The simulator is calibrated against measured data for a wide range of bias conditions and temperature. Material parameters of 4H-SiC are taken from literature and used in the available silicon models of the simulator. The empirical parameters are adjusted to get a good fit between the simulated curves and measured data. The simulation incorporates the bias and temperature dependence of important physical mechanisms like interface trap density, coulombic interface trap scattering, surface roughness scattering and velocity saturation.

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