Ultimate gate oxide thinness set by recombination-tunneling of electrons via Si–SiO2 interface traps

2000 ◽  
Vol 88 (5) ◽  
pp. 2693-2695 ◽  
Author(s):  
S. Kar
Keyword(s):  
Gate Oxide ◽  
Interface Traps

A Comparison of Active Near-Interface Traps in Nitrided and As-Grown Gate Oxides by the Direct Measurement Technique

2020 ◽  
Vol 1004 ◽  
pp. 635-641
Author(s):  
Peyush Pande ◽  
Sima Dimitrijev ◽  
Daniel Haasmann ◽  
Hamid Amini Moghadam ◽  
Philip Tanner ◽  
...  
Keyword(s):  
Nitric Oxide ◽  
Comparative Analysis ◽  
Direct Measurement ◽  
Measurement Technique ◽  
Measurement Method ◽  
Gate Oxide ◽  
Interface Traps ◽  
Gate Oxides ◽  
Mos Capacitors ◽  
Direct Measurement Method

This paper presents a comparative analysis of the electrically active near-interface traps, energetically located above the bottom of conduction band. Two different samples of N-type SiC MOS capacitors were fabricated with gate oxides grown in (1) dry O2 (as-grown) and (2) dry O2 annealed in nitric oxide (nitride). Measurements performed by the direct measurement method revealed that the traps located further away from the SiO2/SiC interface are removed by nitridation. A spatially localized behaviour of NITs is observed only in the nitrided gate oxide but not in the as-grown gate oxide.

Investigation of Oxide Films Prepared by Direct Oxidation of C-Face 4H-SiC in Nitric Oxide

2010 ◽  
Vol 645-648 ◽  
pp. 515-518 ◽  
Author(s):  
Dai Okamoto ◽  
Hiroshi Yano ◽  
Yuki Oshiro ◽  
Tomoaki Hatayama ◽  
Yukiharu Uraoka ◽  
...  
Keyword(s):  
Field Effect ◽  
High Performance ◽  
Room Temperature ◽  
Field Effect Transistors ◽  
Gate Oxide ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Interface Traps ◽  
Direct Oxidation ◽  
Mos Capacitors

Characteristics of metal–oxide–semiconductor (MOS) capacitors and MOS field-effect transistors (MOSFETs) fabricated by direct oxidation of C-face 4H-SiC in NO were investigated. It was found that nitridation of the C-face 4H-SiC MOS interface generates near-interface traps (NITs) in the oxide. These traps capture channel mobile electrons and degrade the performance of MOSFETs. The NITs can be reduced by unloading the samples at room temperature after oxidation. It is important to reduce not only the interface states but also the NITs to fabricate high-performance C-face 4H-SiC MOSFETs with nitrided gate oxide.

scholarly journals Influence of Hydrogen-Nitrogen Hybrid Passivation on the Gate Oxide Film of n-Type 4H-SiC MOS Capacitors

Coatings ◽  
2021 ◽  
Vol 11 (12) ◽  
pp. 1449
Author(s):  
Yifan Jia ◽  
Shengjun Sun ◽  
Xiangtai Liu ◽  
Qin Lu ◽  
Ke Qin ◽  
...  
Keyword(s):  
Photoelectron Spectroscopy ◽  
Gate Oxide ◽  
Sio2 Film ◽  
Interface Traps ◽  
Hydrogen Atoms ◽  
Mos Capacitors ◽  
Bias Stress ◽  
Current Voltage ◽  
Short Time ◽  
Secondary Ion

Hydrogen-nitrogen hybrid passivation treatment for growing high-property gate oxide films by high-temperature wet oxidation, with short-time NO POA, is proposed and demonstrated. Secondary ion mass spectroscopy (SIMS) measurements show that the proposed method causes hydrogen and appropriate nitrogen atoms to accumulate in Gaussian-like distributions near the SiO2/SiC interface. Moreover, the hydrogen atoms are also incorporated into the grown SiO2 layer, with a concentration of approximately 1 × 1019 cm−3. The conductance characteristics indicate that the induced hydrogen and nitrogen passivation atoms near the interface can effectively reduce the density of interface traps and near-interface traps. The current-voltage (I-V), X-ray photoelectron spectroscopy (XPS), and time-dependent bias stress (TDBS) with ultraviolet light (UVL) irradiation results demonstrate that the grown SiO2 film with the incorporated hydrogen passivation atoms can effectively reduce the density of oxide electron traps, leading to the barrier height being improved and the leakage current being reduced.

Improved Reliability With a New Plasma Nh3 Process for 0.35μιη P+ Poly-Gate Nitrided Oxide P-Mosfet's

1996 ◽  
Vol 446 ◽  
Author(s):  
A. Bravaix ◽  
D. Vuillaume ◽  
D. Goguenheim ◽  
V. Lasserre ◽  
A. Straboni ◽  
...  
Keyword(s):  
Gate Oxide ◽  
Barrier Properties ◽  
Oxide Thickness ◽  
Lower Amount ◽  
Interface Traps ◽  
Gate Oxides ◽  
Hot Carrier ◽  
Gate Oxide Thickness ◽  
Donor Type ◽  
Main Influence

AbstractThe electrical properties and the hot-carrier reliability of P+ poly-gate P-MOSFET's are investigated for advanced 0.35 μπι LDD CMOS technologies. It is shown that surface-channel p-devices with an optimized plasma NH3 nitrided gate-oxide have good barrier properties and electrical performances which lead to a higher hot-carrier immunity in 8nm thick nitrided gate-oxides than in pure oxides using DC and AC experiments. The AC stressing shows that reducing the gate-oxide thickness leads to a larger influence of electron detrapping inducing a stronger influence of donor type interface traps than the usual build-up of negative charges. These distinct degradation mechanisms are less significant in nitrided oxide p-MOSFET's due to the lower lateral electric field leading to a lower amount of trapped charges which are quickly suppressed during subsequent detrapping phases leaving the main influence of the interface traps.

The Effect of Nitridation on SiC MOS Oxides as Evaluated by Charge Pumping

2008 ◽  
Vol 600-603 ◽  
pp. 743-746 ◽  
Author(s):  
Daniel B. Habersat ◽  
Aivars J. Lelis ◽  
J.M. McGarrity ◽  
F. Barry McLean ◽  
Siddharth Potbhare
Keyword(s):  
Gate Oxide ◽  
Interface Trap Density ◽  
Interface Trap ◽  
Interface Traps ◽  
Strong Reduction ◽  
Large Shift ◽  
Mos Capacitors ◽  
Charge Pumping ◽  
Nitridation Process ◽  
Flatband Voltage

We have analyzed the effect of post-oxidation nitride anneals (usually with either NO or N2O gases) on SiC MOSFETs. Two 4H:SiC wafers were identically prepared except that one wafer had a nitridation anneal after the gate oxide was formed, while the other was tested as-oxidized. We compared the two processes by making measurements on lateral MOSFETs and MOS capacitors using ID-VGS, C-V, and charge pumping. There was no change in either flatband voltage or interface trap density near the valence band, suggesting that the net fixed charge remained constant (within a few 1011cm-2). However, there was a large shift in the threshold voltage which, when combined with the C-V results, indicates a strong reduction of interface traps near the conduction band of roughly 6.0x1012cm-2 by using the nitridation process. The charge pumping measurements also showed a strong reduction of interface traps. Charge pumping measured a trapping density of 2.5x1012cm-2 for the as-oxidized samples and 5.3x1011cm-2 for the nitrided samples. The frequency-dependence of the charge pumping signal also indicates a spatial distribution of traps, with volumetric trap densities of roughly 1.3x1019cm-3 over 25Å on as-oxidized and 3.8x1018cm-3 over 19Å for nitrided.

scholarly journals The Correlation between the NBTI Effect and the Surface Potential and Density of Interface Traps in Junctionless Nanowire Transistors

2020 ◽  
Vol 15 (2) ◽  
pp. 1-5
Author(s):  
Nilton Graziano Junior ◽  
Renan Trevisoli ◽  
Rodrigo T. Doria
Keyword(s):  
Surface Potential ◽  
Doping Concentration ◽  
Gate Oxide ◽  
Channel Width ◽  
Interface Traps ◽  
Gate Bias ◽  
Nanowire Transistors

This paper discusses the nature of degradation by NBTI effect in MOS junctionless devices when varying the density of interface traps and surface potential. The data obtained in simulations are compared with results from physical devices and it is demonstrated how the quality of gate oxide affects the performance of such transistors, when the density of traps, the channel width, the doping concentration and the gate bias are varied.

Correlation between interface traps and gate oxide leakage current in the direct tunneling regime

2002 ◽  
Vol 81 (2) ◽  
pp. 379-381 ◽  
Author(s):  
Wei Yip Loh ◽  
Byung Jin Cho ◽  
Ming Fu Li
Keyword(s):  
Leakage Current ◽  
Gate Oxide ◽  
Interface Traps ◽  
Direct Tunneling

Correlation Between Gate Induced Drain Leakage and Plasma Induced Interface Traps

1999 ◽  
Vol 592 ◽  
Author(s):  
Siguang Ma ◽  
Yaohui Zhang ◽  
M. F. Li ◽  
Weidan Li ◽  
J. L. F. Wang ◽  
...  
Keyword(s):  
Leakage Current ◽  
Field Enhancement ◽  
Gate Oxide ◽  
Oxide Thickness ◽  
Deep Submicron ◽  
Interface Traps ◽  
Low Field ◽  
Polysilicon Gate ◽  
Gate Oxide Thickness ◽  
Thin Gate Oxide

ABSTRACTIn this paper we carefully investigate the correlation between gate induced drain leakage current and plasma induced damages in the deep submicron p+ polysilicon gate pMOSFETs with gate oxide thickness of 50 Å. Low field enhancement of gate induced drain leakage current caused by plasma charging damage is a function of metal 1 antenna area/length ratio and cell location. Combined with the charge pumping measurements, it is found that gate induced drain leakage current enhancement is mainly due to the plasma induced interface traps. A linear relationship between the gate induced drain leakage and the plasma induced interface trap density is observed within the experimental error. On the other hand, the threshold voltage measurements show that oxide trapped charge has no major contribution to, and no correlation with, the gate induced drain leakage current for thin gate oxide MOSFET devices.

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