Correlation between interface traps and gate oxide leakage current in the direct tunneling regime

2002 ◽  
Vol 81 (2) ◽  
pp. 379-381 ◽  
Author(s):  
Wei Yip Loh ◽  
Byung Jin Cho ◽  
Ming Fu Li
Keyword(s):  
Leakage Current ◽  
Gate Oxide ◽  
Interface Traps ◽  
Direct Tunneling

Correlation Between Gate Induced Drain Leakage and Plasma Induced Interface Traps

1999 ◽  
Vol 592 ◽  
Author(s):  
Siguang Ma ◽  
Yaohui Zhang ◽  
M. F. Li ◽  
Weidan Li ◽  
J. L. F. Wang ◽  
...  
Keyword(s):  
Leakage Current ◽  
Field Enhancement ◽  
Gate Oxide ◽  
Oxide Thickness ◽  
Deep Submicron ◽  
Interface Traps ◽  
Low Field ◽  
Polysilicon Gate ◽  
Gate Oxide Thickness ◽  
Thin Gate Oxide

ABSTRACTIn this paper we carefully investigate the correlation between gate induced drain leakage current and plasma induced damages in the deep submicron p+ polysilicon gate pMOSFETs with gate oxide thickness of 50 Å. Low field enhancement of gate induced drain leakage current caused by plasma charging damage is a function of metal 1 antenna area/length ratio and cell location. Combined with the charge pumping measurements, it is found that gate induced drain leakage current enhancement is mainly due to the plasma induced interface traps. A linear relationship between the gate induced drain leakage and the plasma induced interface trap density is observed within the experimental error. On the other hand, the threshold voltage measurements show that oxide trapped charge has no major contribution to, and no correlation with, the gate induced drain leakage current for thin gate oxide MOSFET devices.

Development of high k/III-V (InGaAs, InAs, InSb) structures for future low power, high speed device applications

2013 ◽  
Vol 1538 ◽  
pp. 291-302
Author(s):  
Edward Yi Chang ◽  
Hai-Dang Trinh ◽  
Yueh-Chin Lin ◽  
Hiroshi Iwai ◽  
Yen-Ku Lin
Keyword(s):  
Low Power ◽  
Leakage Current ◽  
High Speed ◽  
High Performance ◽  
Gate Oxide ◽  
Chemical Cleaning ◽  
Low Leakage ◽  
Low Leakage Current ◽  
High K ◽  
Cleaning Methods

ABSTRACTIII-V compounds such as InGaAs, InAs, InSb have great potential for future low power high speed devices (such as MOSFETs, QWFETs, TFETs and NWFETs) application due to their high carrier mobility and drift velocity. The development of good quality high k gate oxide as well as high k/III-V interfaces is prerequisite to realize high performance working devices. Besides, the downscaling of the gate oxide into sub-nanometer while maintaining appropriate low gate leakage current is also needed. The lack of high quality III-V native oxides has obstructed the development of implementing III-V based devices on Si template. In this presentation, we will discuss our efforts to improve high k/III-V interfaces as well as high k oxide quality by using chemical cleaning methods including chemical solutions, precursors and high temperature gas treatments. The electrical properties of high k/InSb, InGaAs, InSb structures and their dependence on the thermal processes are also discussed. Finally, we will present the downscaling of the gate oxide into sub-nanometer scale while maintaining low leakage current and a good high k/III-V interface quality.

Evidence of hole direct tunneling through ultrathin gate oxide using P/sup +/ poly-SiGe gate

1999 ◽  
Vol 20 (6) ◽  
pp. 268-270 ◽  
Author(s):  
Wen-Chin Lee ◽  
Tsu-Jae King ◽  
Chenming Hu
Keyword(s):  
Gate Oxide ◽  
Direct Tunneling
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