Elimination of the kink effect in GaAs metal semiconductor field‐effect transistors by utilizing a low‐temperature‐grown buffer layer

1992 ◽  
Vol 61 (8) ◽  
pp. 928-930 ◽  
Author(s):  
Junzi Haruyama ◽  
Norio Goto ◽  
Hitoshi Negishi
Keyword(s):  
Low Temperature ◽  
Buffer Layer ◽  
Field Effect ◽  
Field Effect Transistors ◽  
Kink Effect

Low-temperature sol–gel processed AlOx gate dielectric buffer layer for improved performance in pentacene-based OFETs

RSC Advances ◽  
2016 ◽  
Vol 6 (34) ◽  
pp. 28801-28808 ◽  
Author(s):  
Femi Igbari ◽  
Qi-Xun Shang ◽  
Yue-Min Xie ◽  
Xiu-Juan Zhang ◽  
Zhao-Kui Wang ◽  
...  
Keyword(s):  
Low Temperature ◽  
Buffer Layer ◽  
Field Effect ◽  
Gate Dielectric ◽  
Field Effect Transistors ◽  
Sol Gel ◽  
Organic Field Effect Transistors ◽  
Gel Technique ◽  
Improved Performance

An approach to achieve improved performance in pentacene-based organic field effect transistors (OFETs) using high-k AlOx prepared by a low temperature sol–gel technique as a thin buffer layer on a SiO2 gate dielectric was demonstrated.

scholarly journals Nanonet: Low-temperature-processed tellurium nanowire network for scalable p-type field-effect transistors and a highly sensitive phototransistor array

2021 ◽  
Vol 13 (1) ◽  
Author(s):  
Muhammad Naqi ◽  
Kyung Hwan Choi ◽  
Hocheon Yoo ◽  
Sudong Chae ◽  
Bum Jun Kim ◽  
...  
Keyword(s):  
Low Temperature ◽  
Field Effect ◽  
High Performance ◽  
Field Effect Transistors ◽  
Optical Measurements ◽  
Electrical Performance ◽  
Large Area ◽  
Nanowire Network ◽  
P Type ◽  
Nanowire Networks

AbstractLow-temperature-processed semiconductors are an emerging need for next-generation scalable electronics, and these semiconductors need to feature large-area fabrication, solution processability, high electrical performance, and wide spectral optical absorption properties. Although various strategies of low-temperature-processed n-type semiconductors have been achieved, the development of high-performance p-type semiconductors at low temperature is still limited. Here, we report a unique low-temperature-processed method to synthesize tellurium nanowire networks (Te-nanonets) over a scalable area for the fabrication of high-performance large-area p-type field-effect transistors (FETs) with uniform and stable electrical and optical properties. Maximum mobility of 4.7 cm2/Vs, an on/off current ratio of 1 × 104, and a maximum transconductance of 2.18 µS are achieved. To further demonstrate the applicability of the proposed semiconductor, the electrical performance of a Te-nanonet-based transistor array of 42 devices is also measured, revealing stable and uniform results. Finally, to broaden the applicability of p-type Te-nanonet-based FETs, optical measurements are demonstrated over a wide spectral range, revealing an exceptionally uniform optical performance.

Low Temperature Device Processing Technology for II-VI Semiconductors

1989 ◽  
Vol 161 ◽  
Author(s):  
D.L. Dreifus ◽  
R.M. Kolbas ◽  
B.P. Sneed ◽  
J.F. Schetzina
Keyword(s):  
Low Temperature ◽  
Field Effect ◽  
Field Effect Transistors ◽  
Epitaxial Layers ◽  
Processing Technologies ◽  
Device Processing ◽  
Device Structures ◽  
Lift Off ◽  
Processing Steps

ABSTRACTLow temperature (<60° C) processing technologies that avoid potentially damaging processing steps have been developed for devices fabricated from II-VI semiconductor epitaxial layers grown by photoassisted molecular beam epitaxy (MBE). These low temperature technologies include: 1) photolithography (1 µm geometries), 2) calibrated etchants (rates as low as 30 Å/s), 3) a metallization lift-off process employing a photoresist profiler, 4) an interlevel metal dielectric, and 5) an insulator technology for metal-insulator-semiconductor (MIS) structures. A number of first demonstration devices including field-effect transistors and p-n junctions have been fabricated from II-VI epitaxial layers grown by photoassisted MBE and processed using the technology described here. In this paper, two advanced device structures, processed at <60° C, will be presented: 1) CdTe:As-CdTe:In p-n junction detectors, grown in situ by photoassisted MBE, and 2) HgCdTe-HgTe-CdZnTe quantum-well modulation-doped field-effect transistors (MODFETs).

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