Charge-collection efficiency of GaAs field effect transistors fabricated with a low-temperature grown buffer layer: Dependence on charge deposition profile

2000 ◽  
Vol 47 (3) ◽  
pp. 498-507 ◽  
Author(s):  
D. McMorrow ◽  
A.R. Knudson ◽  
J.S. Melinger ◽  
S. Buchner
Keyword(s):  
Low Temperature ◽  
Buffer Layer ◽  
Field Effect ◽  
Field Effect Transistors ◽  
Collection Efficiency ◽  
Charge Collection ◽  
Charge Collection Efficiency ◽  
Charge Deposition

Low-temperature solution-processed Zn-doped SnO2 photoanodes: enhancements in charge collection efficiency and mobility

RSC Advances ◽  
2014 ◽  
Vol 4 (39) ◽  
pp. 20527-20530 ◽  
Author(s):  
Sambhaji S. Bhande ◽  
Dipak V. Shinde ◽  
Shoyebmohamad F. Shaikh ◽  
Swapnil B. Ambade ◽  
Rohan B. Ambade ◽  
...  
Keyword(s):  
Low Temperature ◽  
Collection Efficiency ◽  
Charge Collection ◽  
Solution Processed ◽  
Charge Collection Efficiency ◽  
Temperature Solution

Zn-doped SnO2 photoanodes with enhanced charge collection efficiency and mobility as compared to pristine photoanodes when used in DSSC applications are explored.

Low-temperature sol–gel processed AlOx gate dielectric buffer layer for improved performance in pentacene-based OFETs

RSC Advances ◽  
2016 ◽  
Vol 6 (34) ◽  
pp. 28801-28808 ◽  
Author(s):  
Femi Igbari ◽  
Qi-Xun Shang ◽  
Yue-Min Xie ◽  
Xiu-Juan Zhang ◽  
Zhao-Kui Wang ◽  
...  
Keyword(s):  
Low Temperature ◽  
Buffer Layer ◽  
Field Effect ◽  
Gate Dielectric ◽  
Field Effect Transistors ◽  
Sol Gel ◽  
Organic Field Effect Transistors ◽  
Gel Technique ◽  
Improved Performance

An approach to achieve improved performance in pentacene-based organic field effect transistors (OFETs) using high-k AlOx prepared by a low temperature sol–gel technique as a thin buffer layer on a SiO2 gate dielectric was demonstrated.

scholarly journals Nanonet: Low-temperature-processed tellurium nanowire network for scalable p-type field-effect transistors and a highly sensitive phototransistor array

2021 ◽  
Vol 13 (1) ◽  
Author(s):  
Muhammad Naqi ◽  
Kyung Hwan Choi ◽  
Hocheon Yoo ◽  
Sudong Chae ◽  
Bum Jun Kim ◽  
...  
Keyword(s):  
Low Temperature ◽  
Field Effect ◽  
High Performance ◽  
Field Effect Transistors ◽  
Optical Measurements ◽  
Electrical Performance ◽  
Large Area ◽  
Nanowire Network ◽  
P Type ◽  
Nanowire Networks

AbstractLow-temperature-processed semiconductors are an emerging need for next-generation scalable electronics, and these semiconductors need to feature large-area fabrication, solution processability, high electrical performance, and wide spectral optical absorption properties. Although various strategies of low-temperature-processed n-type semiconductors have been achieved, the development of high-performance p-type semiconductors at low temperature is still limited. Here, we report a unique low-temperature-processed method to synthesize tellurium nanowire networks (Te-nanonets) over a scalable area for the fabrication of high-performance large-area p-type field-effect transistors (FETs) with uniform and stable electrical and optical properties. Maximum mobility of 4.7 cm2/Vs, an on/off current ratio of 1 × 104, and a maximum transconductance of 2.18 µS are achieved. To further demonstrate the applicability of the proposed semiconductor, the electrical performance of a Te-nanonet-based transistor array of 42 devices is also measured, revealing stable and uniform results. Finally, to broaden the applicability of p-type Te-nanonet-based FETs, optical measurements are demonstrated over a wide spectral range, revealing an exceptionally uniform optical performance.

3D imaging of radiation damage in silicon sensor and spatial mapping of charge collection efficiency

2013 ◽  
Vol 8 (03) ◽  
pp. C03023-C03023 ◽  
Author(s):  
M Jakubek ◽  
J Jakubek ◽  
J Zemlicka ◽  
M Platkevic ◽  
V Havranek ◽  
...  
Keyword(s):  
Radiation Damage ◽  
3D Imaging ◽  
Collection Efficiency ◽  
Charge Collection ◽  
Spatial Mapping ◽  
Charge Collection Efficiency ◽  
Silicon Sensor
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