Low power, high speed, charge recycling CMOS threshold logic gate

2001 ◽  
Vol 37 (17) ◽  
pp. 1067 ◽  
Author(s):  
P. Celinski ◽  
J.F. López ◽  
S. Al-Sarawi ◽  
D. Abbott
Keyword(s):  
Low Power ◽  
High Speed ◽  
Logic Gate ◽  
Threshold Logic ◽  
Charge Recycling

High-speed and low-power operation of a resonant tunneling logic gate MOBILE

1998 ◽  
Vol 19 (3) ◽  
pp. 80-82 ◽  
Author(s):  
K. Maezawa ◽  
H. Matsuzaki ◽  
M. Yamamoto ◽  
T. Otsuji
Keyword(s):  
Low Power ◽  
Resonant Tunneling ◽  
High Speed ◽  
Logic Gate ◽  
Power Operation

scholarly journals Low-power high-speed threshold logic and its application to the design of novel carry lookahead adders

2001 ◽  
Author(s):  
Peter Celinski ◽  
Jose F. Lopez ◽  
Said F. Al-Sarawi ◽  
Derek Abbott
Keyword(s):  
Low Power ◽  
High Speed ◽  
Threshold Logic

CMOS differential logic family with self-timing and charge-recycling for high-speed and low-power VLSI

2003 ◽  
Vol 150 (1) ◽  
pp. 45 ◽  
Author(s):  
B.-S. Kong ◽  
J.-D. Im ◽  
Y.-C. Kim ◽  
S.-J. Jang ◽  
Y.-H. Jun
Keyword(s):  
Low Power ◽  
High Speed ◽  
Charge Recycling

scholarly journals An Accumulator using Electron Tunneling Through Tunnel Junction

2021 ◽  
pp. 163-183
Author(s):  
Dr. Anup Kumar Biswas
Keyword(s):  
High Speed ◽  
Electron Tunneling ◽  
Low Cost ◽  
Logic Gate ◽  
Logic Gates ◽  
Threshold Logic ◽  
High Concentration ◽  
Flip Flop ◽  
Linear Threshold ◽  
Parameter Values

Instead of an existing logical Technology, by using an emerging technology we will be able to make an electronic circuit with high speed, low cost, high concentration density, light in weight, reduced gate numbers and low power consumption. This technology is based on the linear threshold logic condition and electron-tunneling event. At the time of implementing a circuit, a multi-inputs but one-output based logic-node will be brought in our consideration. In this work, we have designed a 1-bit accumulator and then implemented it. To develop an accumulator, some small components like 2-input AND, 3-input AND, 3-input OR, 8-input OR, 9-input OR gate and above all a JK Flip-flop (for 1-bit) are to be collected and connected them in logical order to obtain the proper circuit. After verifying all their characteristics with the results obtained from the simulator, we have built a 1-bit accumulator. All the small components are provided in due places. They are analyzed, detected their threshold logic equations, shown their threshold logic gates (TLGs), tabulated their truth tables, drawn their input-output waveforms, given their respective circuits with exact parameter values. In the accumulator, there are nine control variables S1 through S9 in view of performing the operations (i) Addition, (ii) clear, (iii) complement, (iv) AND, (v) OR, (vi) XOR, (vii) Right-shift, (viii) Left-shift and (ix) increment with positive triggering clock pulses. Whether our present work’s circuits are faster or slower with respect to the similar circuits of CMOS based- and Single electron transistor (SET) based circuits are compared and observed that our TLG based circuits are faster than the CMOS and SET based circuits. The power consumed for tunneling event for a circuit is measured and sensed that it would remain in the range of 10meV to 250meV which is low. All the circuits we have presented in this work are of ‘generic multiple input threshold logic gate’ which is elaborately discussed.

Low-power CMOS threshold-logic gate

1995 ◽  
Vol 31 (25) ◽  
pp. 2157-2159 ◽  
Author(s):  
M.J. Avedillo ◽  
E. Jiménez ◽  
J.M. Quintana ◽  
A. Rueda
Keyword(s):  
Low Power ◽  
Logic Gate ◽  
Threshold Logic ◽  
Low Power Cmos

Low Leakage Optimization Techniques for Multi-threshold CMOS Circuits

2020 ◽  
Vol 10 (5) ◽  
pp. 696-708
Author(s):  
Rumi Rastogi ◽  
Sujata Pandey ◽  
Mridula Gupta
Keyword(s):  
Integrated Circuits ◽  
Low Power ◽  
High Speed ◽  
Room Temperature ◽  
Leakage Power ◽  
Optimization Techniques ◽  
Power Gating ◽  
Low Leakage ◽  
Charge Recycling ◽  
A New Technique

Background: With the reducing size of the devices, the leakage power has also increased exponentially in the nano-scale CMOS devices. Several techniques have been devised so far to minimize the leakage power, among which, MTCMOS (power-gating) is the preferred one as it effectively minimizes the leakage power without any complexity in the circuit. However, the power-gating technique suffers from problems like transition noise and delay. In this paper, we proposed a new simple yet effective technique to minimize leakage power in MTCMOS circuits. Objective: The objective of the paper was to propose a new technique which effectively minimizes leakage power in nanoscale power-gated circuits with minimal delay, noise and area requirement so that it can well be implemented in high-speed low-power digital integrated circuits. Methods: A new power-gating structure has been proposed in this paper. The new proposed technique includes three parallel NMOS transistors with variable widths which are functional during the active mode to reduce the on-time delay. A PMOS footer with gate-bias is also connected in parallel with the NMOS footer transistors. The proposed technique has been verified through simulation in 45nm MTCMOS technology to implement a 32 bit adder circuit. Results: The proposed technique offers significant reduction in leakage power, reactivation noise and reactivation energy. The technique reduced the leakage power effectively at room temperature as well as higher temperatures. The reactivation noise produced by the proposed technique minimized by 98.7%, 64.8%, 62.07% and 24.47% as compared to the parallel transistor, variable-width, charge-recycling and the modified-charge recycling techniques respectively at room temperature.The reactivation energy of the proposed technique also minimized by 77.by 77.67%, 55.8%, 45.1%, and 18.32% with respect to the parallel transistor, variable-width, CR and Modified-CR techniques, respectively. Conclusion: The proposed technique offers significant reduction in leakage power, reactivation noise and reactivation energy. The technique reduces the leakage power effectively at room temperature as well as at higher temperatures. Since the delay and area overhead of the proposed structure is minimal, hence it can be easily implemented in high-speed low-power digital circuits.

Low Power High Speed MISTY1 Cryptography Approaches

2018 ◽  
Vol 27 (13) ◽  
pp. 1850200 ◽  
Author(s):  
Abdoul Rjoub ◽  
Ehab M. Ghabashneh
Keyword(s):  
Low Power ◽  
Power Dissipation ◽  
High Speed ◽  
Logic Gate ◽  
Logic Gates ◽  
Portable Devices ◽  
Silicon Area ◽  
Dynamic Power ◽  
Conventional Design ◽  
Reduction Approach

The demand for high performance, low power/secured handheld equipment increased the need for high speed/low energy and efficient encryption/decryption algorithms. Recently, efficient techniques were suggested to increase the standard of security as well as the speed of portable and handheld devices. Also, those techniques cause increment in the lifetime of battery by reducing the total silicon capacitance and minimizing the switching activity. This paper presents two approaches to reduce the number of logic gates at S7 and S9 of MISTY1 in order to reduce the total delay time, power dissipation and silicon area. The Logic Gate Reduction Approach (LGRA) reduces the number of logic gates by applying Boolean Algebra rules and simplifications, while the Duplicated Gate Reduction Approach (DGRA) removes the redundant XOR and AND logic gates which form the S7 and S9 blocks ciphers. The LGRA approach shows that the throughput enhanced by 21.1% compared to the conventional design, the silicon area reduced by 26.8%, while the dynamic power dissipation is reduced by 21.7% on average. The DGRA approach shows that the throughput enhanced by 3.8% compared to the conventional design, the silicon area reduced by 31.7%, while the dynamic power dissipation is reduced by 27% on average. As a result, the proposed approaches could be fit for next generation of handheld and portable devices.

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