High-speed and low-power operation of a resonant tunneling logic gate MOBILE

1998 ◽  
Vol 19 (3) ◽  
pp. 80-82 ◽  
Author(s):  
K. Maezawa ◽  
H. Matsuzaki ◽  
M. Yamamoto ◽  
T. Otsuji
Keyword(s):  
Low Power ◽  
Resonant Tunneling ◽  
High Speed ◽  
Logic Gate ◽  
Power Operation

Low power, high speed, charge recycling CMOS threshold logic gate

2001 ◽  
Vol 37 (17) ◽  
pp. 1067 ◽  
Author(s):  
P. Celinski ◽  
J.F. López ◽  
S. Al-Sarawi ◽  
D. Abbott
Keyword(s):  
Low Power ◽  
High Speed ◽  
Logic Gate ◽  
Threshold Logic ◽  
Charge Recycling

Low Power High Speed MISTY1 Cryptography Approaches

2018 ◽  
Vol 27 (13) ◽  
pp. 1850200 ◽  
Author(s):  
Abdoul Rjoub ◽  
Ehab M. Ghabashneh
Keyword(s):  
Low Power ◽  
Power Dissipation ◽  
High Speed ◽  
Logic Gate ◽  
Logic Gates ◽  
Portable Devices ◽  
Silicon Area ◽  
Dynamic Power ◽  
Conventional Design ◽  
Reduction Approach

The demand for high performance, low power/secured handheld equipment increased the need for high speed/low energy and efficient encryption/decryption algorithms. Recently, efficient techniques were suggested to increase the standard of security as well as the speed of portable and handheld devices. Also, those techniques cause increment in the lifetime of battery by reducing the total silicon capacitance and minimizing the switching activity. This paper presents two approaches to reduce the number of logic gates at S7 and S9 of MISTY1 in order to reduce the total delay time, power dissipation and silicon area. The Logic Gate Reduction Approach (LGRA) reduces the number of logic gates by applying Boolean Algebra rules and simplifications, while the Duplicated Gate Reduction Approach (DGRA) removes the redundant XOR and AND logic gates which form the S7 and S9 blocks ciphers. The LGRA approach shows that the throughput enhanced by 21.1% compared to the conventional design, the silicon area reduced by 26.8%, while the dynamic power dissipation is reduced by 21.7% on average. The DGRA approach shows that the throughput enhanced by 3.8% compared to the conventional design, the silicon area reduced by 31.7%, while the dynamic power dissipation is reduced by 27% on average. As a result, the proposed approaches could be fit for next generation of handheld and portable devices.

scholarly journals A High-Speed Low-Power Divide-by-3/4 Prescaler using E-TSPC Logic DFFs

Electronics ◽  
2019 ◽  
Vol 8 (5) ◽  
pp. 589 ◽  
Author(s):  
Tianchen Shen ◽  
Jiabing Liu ◽  
Chunyi Song ◽  
Zhiwei Xu
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
High Speed ◽  
Critical Path ◽  
Complementary Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Cmos Process ◽  
Flip Flop ◽  
Mode Control ◽  
Power Operation

A high-speed, low-power divide-by-3/4 prescaler based on an extended true single-phase clock D-flip flop (E-TSPC DFF) is presented. We added two more transistors and a mode control signal to the conventional E-TSPC based divide-by-4 divider to achieve the function of the divide-by-3/4 dual modulus frequency divider. The designed divide-by-3/4 achieved higher speed and lower power operation with mode control compared with the conventional ones. The prescaler was comprised of sixteen transistors and integrates an inverter in the second DFF to provide output directly. The power consumption was minimized due to the reduced number of stages and transistors. In addition, the prescaler operating speed was also improved due to a reduced critical path. We compared the simulation results with conventional E-TSPC based divide-by-3/4 dividers in the same process, where the figure-of-merit (FoM) of the proposed divider was 17.4–75.5% better than conventional ones. We have also fabricated the prescaler in a 40 nm complementary metal oxide semiconductor (CMOS) process. The measured highest operating frequency was 9 GHz with 0.303 mW power consumption under 1.35 V power supply, which agrees with the simulation well. The measurement results demonstrate that the proposed divider achieves high-speed and low-power operation.

scholarly journals XOR Based Carry Select Adder for Area and Delay

2020 ◽  
Vol 5 (6) ◽  
pp. 1615-1621
Author(s):  
Ramyabanu Bobba ◽  
Pooja Illa
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
High Speed ◽  
Design Research ◽  
Logic Gate ◽  
Vlsi Design ◽  
Full Adder ◽  
Low Area ◽  
Carry Select Adder ◽  
Technology Comparison

Low power and area proficient high-speed circuits are the most important areas in VLSI design research. Carry select adder is one of the fastest adders with the low area and power consumption. The paper introduces a 16-bit carry select adder with an optimized multiplexer based full adder circuit using Gate Diffusion Input logic (GDI) technology. Comparison is done on Area, Power and Delay parameters. Our circuit requires only two XOR gates and a multiplexer. In this, each logic gate is designed using GDI technology. This further reduces the transistor count resulting in Area, power, delay and complexity minimization. The proposed 16-bit carry select adder provides better results compared to the conventional 16-bit carry select adder with Area and delay.

Resonant Tunneling Chaos Generator for High-Speed/Low-Power Frequency Divider

1999 ◽  
Vol 38 (Part 2, No. 11B) ◽  
pp. L1321-L1322 ◽  
Author(s):  
Yoichi Kawano ◽  
Shigeru Kishimoto ◽  
Koichi Maezawa ◽  
Takashi Mizutani
Keyword(s):  
Low Power ◽  
Resonant Tunneling ◽  
High Speed ◽  
Frequency Divider ◽  
Chaos Generator ◽  
Power Frequency
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