Generating test patterns for VLSI circuits using a genetic algorithm

1994 ◽  
Vol 30 (10) ◽  
pp. 778-779 ◽  
Author(s):  
M.J. O'Dare ◽  
T. Arslan
Keyword(s):  
Genetic Algorithm ◽  
Vlsi Circuits

scholarly journals Testing and Diagnosis of Delay Faults in Finfet VLSI Circuits using Non-Incremental Genetic Algorithm

2020 ◽  
Vol 9 (2) ◽  
pp. 1673-1679
Keyword(s):  
Genetic Algorithm ◽  
Critical Path ◽  
Research Work ◽  
Propagation Delay ◽  
Vlsi Circuits ◽  
Delay Faults ◽  
Path Delay ◽  
Noise Margin ◽  
Critical Path Delay ◽  
Margin Propagation

FinFet transistors are used in major semiconductor organizations which play a significant role in the development of the silicon industries. Due to few embedded memories and other circuit issues the transistors have specific faults in manufacturing, designing of the circuit etc. This paper presents an advanced test algorithm to diagnose those faults. The circuit with different gates is designed to identify the places having faults. In addition, algorithms such as non-incremental algorithms is used to find critical path, path delay and PDF of Critical path delay and Genetic Algorithm for optimisation of Critical path delay for sensitive test vector and no of iterations. The transfer characteristics curve is plotted along with the delay curve which helps in finding out the simulation parameters such as noise margin, propagation delay. The results in the methodology calculate the probability density function of the critical path by estimating mean, standard deviation and variance. The advantages of the integration of the two algorithms in this paper help in analyzing the specific faults in the circuits and the error correction of the broken link in the path analysis and has enhanced performance. Furthermore, more complicated circuits are analyzed for fault detection with different approach. In this paper the research work on testing, diagnosis, estimation of Critical path and PDF of Critical path delay faults for FinFET based Combinational Circuits for 20nm and 32 nm Technologies are presented for the first time using latest Non Incremental Genetic algorithm.

A NEW REPEATER INSERTION TECHNIQUE FOR THE OPTIMIZATION OF GLOBAL INTERCONNECTS IN NANO-VLSI

NANO ◽  
2009 ◽  
Vol 04 (06) ◽  
pp. 345-350
Author(s):  
DAVOOD FATHI ◽  
BEHJAT FOROUZANDEH
Keyword(s):  
Genetic Algorithm ◽  
Propagation Delay ◽  
Vlsi Circuits ◽  
New Method ◽  
Insertion Technique ◽  
Capacitive Load ◽  
Global Interconnects ◽  
Technology Nodes ◽  
Partitioning Technique ◽  
Energy Delay Product

In this paper, a new method for global interconnects optimization in nanoscale VLSI circuits using unequal repeater (buffer) partitioning technique is presented. The optimization is performed with the energy-delay product minimization at 65, 90, and 130 nm technology nodes and various loads, using the genetic algorithm (GA) of MATLAB. The results show more improvements of the total propagation delay with respect to the traditional equal buffer partitioning technique. This improvement is obvious for 90 and 130 nm, and with increasing capacitive load, the improvement will be achieved for 65 nm.

scholarly journals ATPG for Faults Analysis in VLSI Circuits Using Immune Genetic Algorithm

2012 ◽  
pp. 255-260
Author(s):  
P. K. Chakrabarty ◽  
S. N. Patnaik
Keyword(s):  
Genetic Algorithm ◽  
Test Generation ◽  
Pattern Generation ◽  
Vlsi Circuits ◽  
Test Sequence ◽  
Automatic Test Pattern Generation ◽  
Delay Faults ◽  
And Performance ◽  
Test Vectors ◽  
Timing Behaviour

As design trends move toward nanometer technology, new Automatic Test Pattern Generation (ATPG)problems are merging. During design validation, the effect of crosstalk on reliability and performance cannot be ignored. So new ATPG Techniques has to be developed for testing crosstalk faults which affect the timing behaviour of circuits. In this paper, we present a Genetic Algorithm (GA) based test generation for crosstalk induced delay faults in VLSI circuits. The GA produces reduced test set which contains as few as possible test vector pairs, which detect as many as possible crosstalk delay faults. It uses a crosstalk delay fault simulator which computes the fitness of each test sequence. Tests are generated for ISCAS’85 and scan version of ISCAS’89 benchmark circuits. Experimental results demonstrate that GA gives higher fault coverage and compact test vectors for most of the benchmark circuits.

scholarly journals A genetic algorithm approach for global routing of VLSI circuits

2018 ◽  
Vol 7 (2.21) ◽  
pp. 394
Author(s):  
D Ravikumar ◽  
Arun Raaza ◽  
V Devi ◽  
E Gopinathan
Keyword(s):  
Genetic Algorithm ◽  
Cost Function ◽  
Large Scale ◽  
Vlsi Design ◽  
Physical Design ◽  
Vlsi Circuits ◽  
Routing Problem ◽  
Performance Requirements ◽  
Genetic Algorithm Approach ◽  
The Cost

Very Large Scale Integrating (VLSI) design has the objectives of producing the layout for integrating circuits. The currently prevalent submicron regions require innovative, new physical design algorithms. Performance requirements have not seen before, become the significant features of such regions. The last ten years have been witnessing the feature of swelling success of Genetic Algorithms in their application to VLSI physical design. These algorithms are in spot light and the subject matter of study and examination. Routing problem is posed to a cost function which takes care of the total net length, the channel capacity exceedance and crosstalk. The Genetic algorithm is used for optimizing the cost function.  

scholarly journals Generating Test Patterns for Multiple Fault Detection in VLSI Circuits using Genetic Algorithm

2011 ◽  
pp. 139-142
Author(s):  
Balasubramanian R ◽  
Goutham K ◽  
Jenitha S ◽  
Rahul R M ◽  
Thirupathie Raja B ◽  
...  
Keyword(s):  
Genetic Algorithm ◽  
Test Pattern ◽  
Complex Problem ◽  
Pattern Generation ◽  
Vlsi Circuits ◽  
Optimum Number ◽  
Automatic Test Pattern Generation ◽  
Combinational Circuits ◽  
Problem Space ◽  
Test Sets

In this paper we propose a method for the automatic test pattern generation for detecting multiple stuck-at-faults in combinational VLSI circuits using genetic algorithm (GA). Derivation of minimal test sets helps to reduce the post-production cost of testing combinational circuits. The GA proves to be an effective algorithm in finding optimum number of test patterns from the highly complex problem space. The paper describes the GA and results obtained for the ISCAS 1989 benchmark circuits.

A Genetic Algorithm for Channel Routing in VLSI Circuits

1993 ◽  
Vol 1 (4) ◽  
pp. 293-311 ◽  
Author(s):  
Jens Lienig ◽  
K. Thulasiraman
Keyword(s):  
Genetic Algorithm ◽  
Design Process ◽  
Physical Design ◽  
Vlsi Circuits ◽  
Genetic Operators ◽  
Channel Routing ◽  
Genetic Encoding ◽  
Representation Scheme ◽  
Better Than

A new genetic algorithm for channel routing in the physical design process of VLSI circuits is presented. The algorithm is based on a problem-specific representation scheme and problem-specific genetic operators. The genetic encoding and our genetic operators are described in detail. The performance of the algorithm is tested on different benchmarks, and it is shown that the results obtained using the proposed algorithm are either qualitatively similar to or better than the best published results.

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